You're supposed to do this with an FPGA? Write a program in some language (C, C++, Python, Perl... doesn't matter, as long as you're familiar with it) that generates the following output.
First, the preamble:
input [6:0] setting,
output [3:0] tens,
output [3:0] ones
Then, for each number from 0 to 99, generate this group of lines:
tens = 4'd_;
ones = 4'd_;
Fill in the appropriate values where the
_ are. A Python example:
for k in range(100):
print " 7'd%d: begin" % k
print " tens = 4'd%d;" % (k // 10)
print " ones = 4'd%d;" % (k % 10)
print " end"
Finally, the postamble:
tens = 4'hX;
ones = 4'hX;
Now you save this as a Verilog .v file and feed it to your FPGA compiler and let it do the dirty work.
Many, many things in FPGAs reduce to "write the code in whatever way solves the problem without too much fuss and let the compiler do the dirty work." Code generator programs are your friends.