Dividing a clock down in Verilog is a basic exercise, and there are loads of answers online about how to do it. What I want to know is whether it is OK to use a clock that has been divided down using verilog on a real FPGA to clock flip flops.
I'm asking because common knowledge dictates that we should never put combinational logic on a clock line and then use the resulting signal to drive a flip flop's clock.
Sure, a clock divider isn't what we would call combinational logic, but at the end of the day, I would still be putting logic gates between a (presumably) complex clock network and the clock signal of a flip-flop.
It's worth noting that I've certainly done this in some hardware projects and it has worked, but it was on a low performance FPGA. I'm wondering if this would work consistently and reliably on most FPGAs, or if I just got lucky with the chip I was using.