Dividing a clock in Verilog - is it OK?

Question

Dividing a clock down in Verilog is a basic exercise, and there are loads of answers online about how to do it. What I want to know is whether it is OK to use a clock that has been divided down using verilog on a real FPGA to clock flip flops.

I'm asking because common knowledge dictates that we should never put combinational logic on a clock line and then use the resulting signal to drive a flip flop's clock.

Sure, a clock divider isn't what we would call combinational logic, but at the end of the day, I would still be putting logic gates between a (presumably) complex clock network and the clock signal of a flip-flop.

It's worth noting that I've certainly done this in some hardware projects and it has worked, but it was on a low performance FPGA. I'm wondering if this would work consistently and reliably on most FPGAs, or if I just got lucky with the chip I was using.

Answer 1

Theres a few things to consider

1. The chip needs to actually have the routing to bring a clock signal from a register output into a clock net. Most FPGAs i've worked with can but do check.

2. Clock nets are a limited resource, while some chips can clock flip flops off normal nets doing so is likely to have worse timing behaviour.

3. You are likely to need to manually tell the timing analyser what you are doing to get proper timing behaviour/analysis, the details of this are likely to be chip specific.

4. There is likely to be substantial phase-skew between the original clock and the generated clock.

5. To ensure the clock is clean it should come directly from a register output, not from combinatorial logic.

Overall you can do it but I would consider it a last resort. Most of the time you can get similar results with a lot less headaches by using enable signals and/or by using multiple outputs from the chip's pll.