I get this Warning from Altera Design Assistant for the below:

Clock port and any other port of a register should not be driven by the same signal source

Critical Warning (308012): Node "App_Logic:inst1|LGVCtrl:inst1|i_Skal:inst|s_clk"

I previously made some changes to this to meet Timing requirements. I tried driving just a '1' instead of driving the sys_clk to v_clk. But the timing requirements do not meet when I do so. Any suggestions?


I haven't tried to understand what your code is trying to do here, but your error shows a misunderstanding of one of the fundamentals of how your code will run:

v_clk := sys_clk; -- '1';

You have assumed that because your process works from the rising edge of sys_clk, that when your code reaches this point, sys_clk will have the value of '1'. This will be true in simulation, but in the real hardware, there is no way that this value of '1' will make the setup time for the register you have described. This is made worse by the path from your FPGA's clock network for sys_clk to the register being shorter than to the data pin. Additionally, it is bad practice to use a clock as data, and this in itself is prone to timing problems.

Moving on to the actual functionality, the only assignment to v_clk is the line above, so why is this signal not simply '1'?

I think if you understand these issues and revise your design, your problem will probably go away.

  • \$\begingroup\$ Will a v_clk= '1' not going to be a 1 on the lpm_divider clock throughout ?(but yes, a rising edge of sys clock will also drive only 1 on the divider clock I suppose). Is there a way/ is it necessary to toggle the divider clock? A negative hold slack arises when a 1 is driven to v_clk. \$\endgroup\$ – Alex Krish Apr 5 '16 at 9:13
  • \$\begingroup\$ @AlexKrish have you simulated this design at all? v_clk and s_clk always being '1' after the first sys_clk edge probably isn't what you wanted. I would say you should arrive at a design that works in simulation before worrying about whether your timing constraints are met. \$\endgroup\$ – scary_jeff Apr 5 '16 at 9:20
  • \$\begingroup\$ I agree with other comments. Please take your time to build your knowledge from solid ground. Start with simple combinatorial logic, then a FF, then a register, a counter, etc. Your code writing style shows you have not grasped the essence of VHDL, which is, to DESCRIBE Hardware. VHDL is NOT a software programming language. \$\endgroup\$ – Claudio Avi Chami Apr 5 '16 at 18:41

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