I haven't tried to understand what your code is trying to do here, but your error shows a misunderstanding of one of the fundamentals of how your code will run:
v_clk := sys_clk; -- '1';
You have assumed that because your process works from the rising edge of
sys_clk, that when your code reaches this point,
sys_clk will have the value of
'1'. This will be true in simulation, but in the real hardware, there is no way that this value of
'1' will make the setup time for the register you have described. This is made worse by the path from your FPGA's clock network for
sys_clk to the register being shorter than to the data pin. Additionally, it is bad practice to use a clock as data, and this in itself is prone to timing problems.
Moving on to the actual functionality, the only assignment to
v_clk is the line above, so why is this signal not simply
I think if you understand these issues and revise your design, your problem will probably go away.