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In this circuit:

schematic

simulate this circuit – Schematic created using CircuitLab

As soon as power on, the transistor will start conducting in saturation. This will make V1 ~ 100mV (\$ Vce_{sat}\$). Since initially there is no charge on the capacitor, V2 will be equal to 100mV as well.

But suppose that we wait. AFAIK, transistor will not leave the saturation no matter how much we wait. Hence, V2 will always be 100mV.

But after we wait a sufficient (long) amount of time, will V1 be equal to 9V, giving a voltage drop of 8.9V over the capacitor, or will it be 9.1V, giving a voltage drop of 9V over the capacitor (or will it be something else)?

In either case, could you explain why this is the case?

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Despite what the other answers suggest, this is not an oscillator !

Edit: it appears the schematic was more complex before and then it was or contained an oscillator.

Note how C1 and R2 are just in parallel with R1, which is the collector resistor.

A long time after you switch on this circuit (apply 9 V supply) the capacitor will be charged to whatever the voltage difference V1 - V2 is so you can consider C1 not to be there.

V1 is then easy, as it connects only through R2 to 9V, V1 = 9V

For V2 you have to calculate the current through R1. This is more complex as this current depends on the values of R1 and R3 and the mode of operation of TR1 (in saturation or out of saturation).

The easiest is to assume that TR1 is not in saturation, then Ic/Ib = beta. Assume Vbe of TR1 to be about 0.7 V then V(R3) = 9 - 0.7 = 6.3 V. Now Ib can be determined, multiply by beta and you have Ic. Then calculate V(R1) = Ic * R1 Now you can calculate V2. Now also check that V2 has a realistic value, if V2 is between 0.5 - 9 V then TR1 can operate out of saturation. If V2 is lower than the VCE of TR1 will be low and it will be forced into saturation. Then you will have to make a solution for the saturation case. But then VCE must be given.

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  • \$\begingroup\$ If we assume that transistor operates in saturation and \$ Vce_{sat} = 100mV \$, then after a long time, V2 = 100mV and V1 = 9V, giving a voltage drop of 8.9V over the capacitor right? \$\endgroup\$ – Utku Apr 6 '16 at 8:41
  • \$\begingroup\$ That is correct. \$\endgroup\$ – Bimpelrekkie Apr 6 '16 at 8:49
  • \$\begingroup\$ Thanks. At first I thought that net voltage drop over the cap shoud be 9V (i.e. the supply voltage) no matter what but apparently it is not that way. This raises more questions about capacitor behavior on circuit with many different kinds of elements but I think that it is worth of another question. \$\endgroup\$ – Utku Apr 6 '16 at 9:02
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Below part applies to the complete linked circuit (astable multivibrator) with the parts connected to it:

V1 cannot exceed about 0.7V because it is connected to the base of the other transistor TR2.

When the TR2 turns on, it will turn TR1 off through C2 (when TR2 collector drops to 0.1V).

The cycle then repeats, assuming the oscillator has started properly.

Without some kind of transient to start the oscillator it's possible to have both transistors 'on' and no oscillation, and typically that's what you might see in a simulation where the parts are exactly matched. It's also possible to happen in real life- the gain of the transistors in saturation is very low so there is no guarantee it will start.


This part applies to the fragment in isolation, without the other parts attached.

Edit: without the transistor TR2, and with TR1 saturated, V2 will change as C1 charges (from 0.1V) toward the supply voltage with time constant \$\tau= R_2 C_1\$. It will never quite get there, but after a long time it will be 'close enough'.

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  • \$\begingroup\$ Yes in the astable, that will happen but consider only the circuit I have given the diagram for. \$\endgroup\$ – Utku Apr 6 '16 at 6:48
  • \$\begingroup\$ V1 will charge asymptotic to the supply voltage without the transistor TR2. \$\endgroup\$ – Spehro Pefhany Apr 6 '16 at 6:52
  • \$\begingroup\$ I couldn't understand what that means. Could you edit the answer if possible please? \$\endgroup\$ – Utku Apr 6 '16 at 6:54
  • \$\begingroup\$ So will V2 stay constant at 0.1V and V1 will approximate to 8.9V or 9V? \$\endgroup\$ – Utku Apr 6 '16 at 7:03
  • \$\begingroup\$ Yes, that's right. \$\endgroup\$ – Spehro Pefhany Apr 6 '16 at 7:21
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electronics is tough. the voltage v1 is 100mv as you say if the capacitance charge is zero. But as the capacitor gets charged towards 9V, the transistor will conduct and keep the voltage to a value not much higher than 100mv, say 100mV. Do not forget that the transistor is behind the capacitor and you cannot assume that the capacitor is independent of what the transistor does. In actual; case, the capacitor will charge towards negative voltage if permitted, as in that case, the transistor will be in cut off. In general you cannot split the circuit as you have done because what is facing the voltage v1 is not known once you split. Be aware that it faces another base and a lot of things depend on that. the base is the control point and hence you should not neglect its presence when you split. a voltage of 100V can cause a problem if the current you draw is in excess of max current. If the resistance is say 1meg, the current is only 100uA and too less to cause the problem. But if you happen to perspire, the resistance can become much lesser and current can increases to lethal levels. So always look not just at the voltage but also its source resistance. If the 100v has an inherent resistance of 1meg associated with it, you get 50V when your resistance is 1meg, and current is 50uA. If your resistance reduces to even 10k, the current is not much higher as the TOTAL resistance is 10k+1meg, which is internal; resistance of source. So you will have no harm. that is why you can use a neon to check the presence of mains voltage. Summary always be aware of resistance of source.. Do not just think that it is low. Check the actual value. that is why I say "behind", as other components existing in the circuit do matter for analysis.

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  • \$\begingroup\$ But what about the voltages V1 and V2 when we wait a long time? Please consider only the circuit I have given the diagram for (assume that I have not talked about astable at all). \$\endgroup\$ – Utku Apr 6 '16 at 6:53
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    \$\begingroup\$ -1 For a confusing and unstructured answer and over complicating things. \$\endgroup\$ – Bimpelrekkie Apr 6 '16 at 8:53

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