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Assumptions:

  1. Computer architecture: Describes how the different modules of a processor interact with each other.

  2. A computer architecture is defined using vhdl files

  3. Computer Organization: Describes the physical layout of the processor modules on silicon.

  4. A computer organization is defined using a set of photo masks (and manufacturing process eg chemical, that goes at each step)

  5. Computer Organization, therefore, requires that the fab process be taken into account.

  6. ARM is not in the fabrication business, therefore it does not sell photo masks.


My question(s):

  1. What exactly is ARM selling to a vendor (eg: freescale)?
  2. For a SoC (System On Chip), (eg: iMx6), which part is ARM and which is Freescale? Who did the integration?
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    \$\begingroup\$ It can be even more complex with 3 companies involved: ARM designs the IP for CPU, Qualcomm designs a product (SOC) with that and then has that chip made at TSMC. It is also possible that TSMC also does the physical layout generation so not Qualcomm. \$\endgroup\$ – Bimpelrekkie Apr 6 '16 at 17:37
  • \$\begingroup\$ ARM sells their processor cores, they give you the source code (definitely in verilog, perhaps vhdl I dont know about that), with a lot of rules and fees. The processors stop at the AMDA/AXI bus, someone else or some other code is required to connect that processor to other things in the chip. ARM does/has sold other things that help with an SoC but the main thing is the processors. \$\endgroup\$ – old_timer Apr 7 '16 at 0:42
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You're using those terms wrong. "Computer organization" is a rarely-used term for the microarchitecture, and "computer architecture" is a superset of that.

Integrated circuit IP blocks come in two basic forms:

  • A soft macro is the RTL (VHDL or Verilog) that describes the functional implementation of the IP. This is compiled into a gate-level netlist, which is then turned into a physical layout to produce the mask set for manufacturing. Here's an example from Cadence -- an Ethernet MAC. When you buy it, you get Verilog files, documentation, and a Verilog testbench for verification.

  • A hard macro is a physical layout of the IP suitable for a given process. It's added to the larger chip layout as a single block, which saves some steps in the design process. Here's another Cadence example -- an Ethernet PHY. It's offered in 180nm and 130nm processes at TSMC, UMC, and SMIC, and is delivered to the customer in the form of GDSII layout files.

ARM sells both of these. The MCUs I've worked on usually use soft macros of ARM Cortex CPUs. We had some older product with ARM7 hard macros, but I don't know if they were hardened by ARM or us. Today, ARM has hard macro versions of the Cortex-A series listed on their web site. Most of their products are synthesizable (soft macros), though. It looks like you can download the (soft) Cortex-M0 for free for non-commercial use on the ARM DesignStart site.

In an SoC, the ARM part is just the CPU. (The designer can also buy peripheral IP from ARM, but it's not required.) The SoCs I've worked on have a mix of third-party and internal IP.

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    \$\begingroup\$ ARM also licenses the architecture for custom designs (e.g., Qualcomm's Kyro in the Snapdragon 820). Hard macros may also be more highly optimized (for a given target) than common tools will provide (Processor Optimization Pack). In theory, a hard macro can use full custom design, but optimizing relatively few components (especially memory components) provides much of the benefit for less cost. \$\endgroup\$ – Paul A. Clayton Apr 6 '16 at 19:44
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  1. What exactly is ARM selling to a vendor (eg: freescale)?

A license to sell chips that include ARM intellectual property.

  1. For a SoC (System On Chip), (eg: iMx6), which part is ARM

The definition of the CPU core(s) and their interfaces.

... and which is Freescale?

The physical implementation, including the design of any peripheral logic included on the chip.

Who did the integration?

Freescale, of course.

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    \$\begingroup\$ "The definition of the CPU core(s) and their interfaces".. can you please elaborate on what is meant by "definition", does that include the vhdl of the core, or is this left to freescale to figure out? \$\endgroup\$ – aiao Apr 6 '16 at 16:52
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    \$\begingroup\$ Yes, the definition undoubtedly includes an HDL (not necessarily VHDL) description of the core, because that is the least ambiguous way to convey that kind of information. \$\endgroup\$ – Dave Tweed Apr 6 '16 at 17:21
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When I was involved in a chip design project which involved integrating an ARM, what we got was netlist Verilog. That is, a complete list of the gates and connections that make up the chip, but not in a higher-level form suitable for easy modification.

We then did our own placement and routing. This is usually necessary on each project as the shape of the chip area allocated to ARM will be different.

I believe multiple levels of license are available so you could buy a placed core in a standard shape already to save time.

(Placed netlists are exactly as they sound: a list of gates and their locations.)

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    \$\begingroup\$ "complete list of the gates and connections that make up the chip" - that must be one hell of a list. \$\endgroup\$ – Rev1.0 Apr 6 '16 at 18:33
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    \$\begingroup\$ It's not that bad - Cortex M0 is only 12K gates. It's the big GPU designs that are the struggle .. \$\endgroup\$ – pjc50 Apr 6 '16 at 19:58
  • \$\begingroup\$ I thought a "core" is millions or billions of gates? The Intel 4004 was reportedly named because it has that many gates. \$\endgroup\$ – JDługosz Apr 6 '16 at 21:35
  • \$\begingroup\$ @JDługosz: The Intel 4004 has 2,300 transistors, according to one transistor count list. \$\endgroup\$ – davidcary Apr 6 '16 at 23:06
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    \$\begingroup\$ @JDlugosz The processing pipeline for arm is short and the cache and supporting on die peripherals (large contributor to transistor count) are seperate from the core ip (you connect them to the bus). The full SOC/ASIC will have a much larger gate count. A device like an x86 has an additional microcode layer and a much longer (10x) pipeline requiring e.g. more complex branch prediction as well as on die cache and recently on die MMU \$\endgroup\$ – crasic Apr 7 '16 at 2:23
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ARM sells intellectual property (IP) to other companies. In your example, Freescale purchases the rights to use ARM IP, namely the processor core. What is the "core"? The core is just about anything that isn't a peripheral, like a SPI driver or an ADC or DAC. As part of the core, ARM included hardware systems to act as bridges between the actual processor stuff and the customer's peripheral.

As far as deliverables, ARM does not provide a complete HDL to the customer. They provide high-level abstractions that the end user's HDL can link against (HDL wrappers), and they also likely provide the physical layout of the core.

ARM sells more than just processor cores, they also have a whole segment of complex IP that are not processors. When ARM sells a processor core, they get money up front and/or they get royalties on all the devices sold with their designs in them. It's a pretty good deal for them, considering there are about 10 billion ARM processors in the wild.

To sum up:

  • ARM sells IP (designs basically) to customers to integrate into their end product
  • SoC makers like Freescale design their own peripherals for the ARM core.
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