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I'm writing VHDL code for a filter which I want to implement on a Spartan 6 FPGA. When I tried running a testbench for my code, one of the processes entered an infinite loop, so I added a wait statement before the "end process;" statement, but after some research I found that the wait statement is not synthesisable so it is good only for simulation purposes using testbenches. Can anyone suggest an alternative to the wait statement so that my code becomes synthesisable on an FPGA? Thanks in advance!

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A clock and a counter.

Where you enter the wait state, you set the counter, then decrement it on every clock cycle, and when it reaches zero, you exit the wait state.

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  • \$\begingroup\$ And if the delay is less than the clock period, you can instantiate combinational elements as a sort of delay chain, though that is a bit hacky to do on FPGAs. \$\endgroup\$ – Ironil Apr 7 '16 at 8:32
  • \$\begingroup\$ There is a reason why we actually test our designs at 0°C and at 55°C. -_- \$\endgroup\$ – Simon Richter Apr 7 '16 at 12:43

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