I'm using external names introduced in VHDL-2008 to access a bunch of signals (let's say 1000) in a design hierarchy with many levels.

<< signal dut.signal_1 : std_logic >>  
<< signal dut.signal_2 : std_logic >>  
<< signal dut.signal_1000 : std_logic >>

I want to iterate over these 1000 signals and force them to '0' or '1' to perform some fault testing and it would therefore be convenient to have something like this pseudo code:

alias test_vector : std_logic_vector(999 downto 0) is (dut.signal_1, dut.signal_2, ..., dut.signal_1000)

I.e. I want to construct an "alias-vector" with all my external names in it. With this vector I can do something like this:

test_vector(random_number) <= force '0';

I can't seem to find an easy way of doing this. The only way I can think of is to use one alias and with a script copy the external names one at a time into the file, run the simulation and then repeat for all 1000 signals.

Any help or ideas are much appreciated!

  • \$\begingroup\$ Why do you have single bit signals instead of a 1000 bit vector? Currently, there is no way to iterate such signals. VHDL-2017 will maybe have a feature to iterate over record elements, but I don't know if it could be extended to such a use case. \$\endgroup\$ – Paebbels Apr 7 '16 at 20:01
  • \$\begingroup\$ The single bit signals are various signals in the hierarchy, like the bits in a 5-bit counter for example. I want to inject faults at random places in the design (preferably in all available nodes/bits) \$\endgroup\$ – sandberg Apr 7 '16 at 20:06
  • \$\begingroup\$ Maybe you should use records to group the external signals \$\endgroup\$ – Claudio Avi Chami Apr 8 '16 at 14:28
  • \$\begingroup\$ Does it solve your needs? I would like to be updated because we are looking into similar problems. \$\endgroup\$ – Paebbels Apr 13 '16 at 20:01
  • \$\begingroup\$ To get something working quickly I'm currently reading a text file with the paths of all interesting signals in the hierarchy and using this information together with $signal_force and $init_signal_spy in my system-verilog test bench. Still looking into using cocotb or something similar to get a more "standardized" way of doing it. My method at the moment is very simulator dependent. \$\endgroup\$ – sandberg Apr 13 '16 at 20:20

Maybe you should look for the VHPI interface (VHDL Procedural Interface).

Testing frameworks like Cocotb use this standardized API to connect a simulator like QuestaSim/ModelSim, Riviera-PRO or ... to an external programming language like Python.

So the testbench is written in Python code and it connects via VHPI to the DUT. The stimuli is generated by Pathon code and the results are transferred back to Python for checking. VHPI has the ability to access every signal and of course iterate over every "node" in the design. It can also force/drive signals.

So you could compile your own VHPI tool or maybe extend Cocotb to access signal beneath the top-level. If I interpretate this right, Cocotb can already access deep signals: Quickstart:Accessing the Design

Related questions:

  • \$\begingroup\$ Thanks, this looks promising. From the information I could find the use of simulation commands or an external interface outside of VHDL seems to give better controllability. I'll mark this as an accepted answer in case no one else comes with a better solution \$\endgroup\$ – sandberg Apr 8 '16 at 9:13

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