I'm using external names introduced in VHDL-2008 to access a bunch of signals (let's say 1000) in a design hierarchy with many levels.
<< signal dut.signal_1 : std_logic >> << signal dut.signal_2 : std_logic >> ... << signal dut.signal_1000 : std_logic >>
I want to iterate over these 1000 signals and force them to '0' or '1' to perform some fault testing and it would therefore be convenient to have something like this pseudo code:
alias test_vector : std_logic_vector(999 downto 0) is (dut.signal_1, dut.signal_2, ..., dut.signal_1000)
I.e. I want to construct an "alias-vector" with all my external names in it. With this vector I can do something like this:
test_vector(random_number) <= force '0';
I can't seem to find an easy way of doing this. The only way I can think of is to use one alias and with a script copy the external names one at a time into the file, run the simulation and then repeat for all 1000 signals.
Any help or ideas are much appreciated!