0
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Why won't the value of output changes? It has been clocked and the inner loop should update? In the simulation, the output's value is always 9. Please help what I may be missing. I would like the code to update output when the inner loop updates.

 library ieee;
    use ieee.std_logic_1164.ALL;
    use ieee.numeric_std.ALL;

entity test is
    port(
        clk : in std_logic;
        output : out integer
    );
end entity;

architecture behave of test is
begin
process(clk)
begin
if (clk'event and clk = '1') then
for x in 0 to 9 loop
   for y in 0 to 9 loop
       output <= y;
   end loop;
end loop;
end if;
end process;
end behave;

I would like to use values of inner and outer loop. It could be used as counter for my system.

The desired waveform would be like this. enter image description here

I would like to use value of y and x if possible/

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1
  • \$\begingroup\$ About the update: You don't need a loop. Just put a counter to increment each clock cycle in the process. \$\endgroup\$
    – Eugene Sh.
    Commented Apr 8, 2016 at 15:07

2 Answers 2

3
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Your process experiences the following stages:

  1. An event is observed on clk.
  2. clk has a value of '1', so the execution proceeds through into your loops
  3. Your loop tries to assign various values to y. Only the last value assigned will be scheduled, this execution of a process with a sensitivty list happens in zero time.
  4. The process ends.

You will not see the value of y counting through different values, because all the 'changes' happen in zero time. You will only observe the final value, which is 9.

Your explanation of what you want the code to do does not really make sense. Are you trying to implement your code in a real FPGA device? In this case, what would it mean for a counter to cycle through the values 0-9 on a rising clock edge? You may need to broaden your description; why do you want the output to do this?


If you just want a counter to count through the values 0..9, you could use something like this:

signal counter_s : integer range 0 to 9 := 0;  -- Initial value of zero

...

process (clk)
begin
  if (rising_edge(clk)) then -- Better to use `rising_edge` function
    if (counter_s = 9) then
      -- The counter should loop back round to zero
      counter_s <= 0;
    else
      counter_s <= counter_s + 1;
    end if;
  end if;
end process;

counter <= counter_s;

You need an intermediate signal counter_s, because a port of mode out cannot be read.

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4
  • \$\begingroup\$ So, the entire execution of the both loops take place within a clock cycle? And the very last loop execution will be updated to the output? \$\endgroup\$
    – Main
    Commented Apr 8, 2016 at 14:37
  • \$\begingroup\$ I would like to update output in each update of inner loop. Thank you. \$\endgroup\$
    – Main
    Commented Apr 8, 2016 at 14:42
  • 1
    \$\begingroup\$ What is the waveform you want to achieve? Draw it together with the clock for your own understanding. \$\endgroup\$
    – Eugene Sh.
    Commented Apr 8, 2016 at 14:43
  • \$\begingroup\$ @Main, yes, the entire loop occurs on each clock cycle. Do you see any code within the loop that says to wait for another clock edge? \$\endgroup\$
    – The Photon
    Commented Apr 8, 2016 at 15:44
0
\$\begingroup\$
begin
process
begin
for x in 0 to 9 loop
   for y in 0 to 9 loop
       wait until (rising_edge(clk));
       output <= y;
   end loop;
end loop;
end process;
end behave;

The code inner workings are connected to the way VHDL runs processes. All process lines are run sequentially and in zero time. To synchronize the process to a clock, one way to achieve this is to force the process to stop and wait for a rising edge on the clock signal. This code is for simulation/testbenches only, not for synthesis.

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9
  • \$\begingroup\$ Mind you! This code is for simulation only. If you want to synthesize it, better check first how HW counters are written \$\endgroup\$ Commented Apr 8, 2016 at 14:38
  • \$\begingroup\$ Could you please provide an explanation of why the code works? \$\endgroup\$
    – Voltage Spike
    Commented Apr 8, 2016 at 15:22
  • \$\begingroup\$ In a few words, for synchronous logic, you have to write the code so it will 'stop' waiting for a clock event. VHDL procedures execute all the lines in 'zero' time, the only wait to make a procedure synchronous is to force it to wait for the clock rising edge. This coding style is for testbench only, not for VHDL synthesis. If you are interested in several examples for registers, counters, etc. with testbench and waveforms you can visit my site here: fpgasite.wordpress.com/2016/04/08/code-snippets-reloaded \$\endgroup\$ Commented Apr 8, 2016 at 15:25
  • 1
    \$\begingroup\$ The explanation ought to be in the answer, comments are not part of the answer. \$\endgroup\$
    – user8352
    Commented Apr 8, 2016 at 23:14
  • \$\begingroup\$ The explanation is also in the answer \$\endgroup\$ Commented Apr 9, 2016 at 4:37

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