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When implementing SPI communication between a master and multiple slaves, there's basically two topologies to choose from: either resend the same data to each slave, or clocking data through all slaves in chain mode.

My question is this: suppose the master needs to continuously shift the contents of a single register into 16 identical slave microcontrollers at the highest possible speed, so not wasting time in resending the same data or clocking bits through all slaves?

Would it be possible to tie all SS (so select all slaves at the same time) and MOSI lines together and completely disregard (or disconnect) all MISO lines if you are not interrested in any data coming back from slave controllers?

Is there a way to achieve this?

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  • \$\begingroup\$ What part is being used for the slaves? When you say "suppose the master needs to continuously shift the contents of a single register into 16 identical slave microcontrollers at the highest possible speed" do you literally mean every clock transition, without end, shifts data into the slaves? Are you providing the code for the slave microcontrollers, or do you have to work with existing code? \$\endgroup\$ – gbulmer Apr 10 '16 at 10:53
  • \$\begingroup\$ Indeed, all slaves are pic32 uC. The idea is to replicate a port state of the master to all slaves, as fast as possible. The ending requires som thought indeed, but as a concept? \$\endgroup\$ – Peterstevens Apr 10 '16 at 11:02
  • \$\begingroup\$ So, are you are writing all of the code for the slaves, or is that beyond your control? \$\endgroup\$ – gbulmer Apr 10 '16 at 11:09
  • \$\begingroup\$ Scratch solution, full control :) \$\endgroup\$ – Peterstevens Apr 10 '16 at 11:09
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When implementing SPI communication between a master and multiple slaves, there's basically two topologies to choose from: either resend the same data to each slave, or clocking data through all slaves in chain mode.

I have no idea what dark corner of the internet you got this from. The standard, most common, and obvious way to handle multiple SPI slaves is for each to have its own slave select line. That's precisely what they are for.

You wire the MOSI, SCK, and MISO lines all together, then each slave gets its own slave select line. The master asserts one of the slave selects at a time, and only that slave is allowed to drive the MISO line.

Same data to all slaves

In the special case of sending the same data to all slaves, you can tie all the slave selects together, or assert them all at the same time.

You do need to handle MISO differently however. Even if all the slaves are supposed to be identical, stuff happens and there could be a conflict. If you never care about returned data from any of the slaves, then you can just leave the individual MISO lines unconnected. Put a pulldown on the master's MISO input so that it is not floating.

Another option is to put pulldowns on all the MISO lines, then run them all into a wide OR gate, then the output of that into the master's MISO input. That allows normal bi-directional communication with individual slaves if you only assert one slave select, and 1 to N output only if you assert multiple slave selects. In that case you just ignore the received data in the master.

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  • \$\begingroup\$ Your second paragraph exactly answers my newbie question. Is it possible to simply disregard the MISO lines: yes. Thanks for the pulldown hint also. The second options sounds creative as well. But there is no value-add if we never care about returned data, is there? Thanks!! \$\endgroup\$ – Peterstevens Apr 10 '16 at 12:29
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Logically, yes.

Physically you might want to pay attention since you state that you want to drive them "at the highest possible speed". Now there's two issues which come to my mind:

  • High clock speeds usually mean fast edges which in turn requires paying attention to echo, ringing, ... all the nice issues you get once you get into high-speed design. Therefore, you want your signal traces to be around 50Ohms to have them terminated properly (does your microcontroller provide some kind of signal termination at its input pins?). Now unless your slaves are located very close to each other and the signal distance is very low, you might get away with your approach, but I wouldn't recommend it. You might see all kinds of effects you probably don't want to.
  • Your master most likely has only a limited output drive capacity (fan-out). You might want to consider using a bus buffer to lessen the burden you're actually putting on it (both capacitance and resistive - wise).
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  • \$\begingroup\$ Thanks for your answer. Indeed, line issues also came to mind. Especially if the slaves are/could be on a daughter boards (allthough densely placed). \$\endgroup\$ – Peterstevens Apr 10 '16 at 12:16

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