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simulate this circuit – Schematic created using CircuitLab
At VM1 I theoretically expect about 1mV. When I connect with the opamp I get a voltage drop of 0.5mV at VM1, I get this values in simulation(theoretically). What is the cause of this (something to do with the 10MOhm) and what can I do to prevent this in the practical circuit.
Edited question for non-inverting case, removed circuit + analysis of negative op-amp amplifier.
Yes the problem is most likely the 10MOhm resistor. This happens because while the op-amp assumption is that $$ I_+ = I_- = 0 $$ this is not really the case, and there is a small input current.
You should decrease the size of both voltage divider resistors while keeping their ratio the same. This will give the required attenuation while also allowing the op-amp terminals to sink some current.
You can look at the datasheet to see how much current the op-amp inverting/non-inverting terminals actually draw. You want this current to make only a small difference compared to the voltage you are amplifying.
I will say that trying to amplify a 500uV signal like this is going to create a lot of noise, and the voltage divider will draw a lot of power. A better way is probably to control the gain with the feedback resistor ratio rather than pre-attenuate it like this, especially for a 1V signal.
