I have Verilog's code. It is simulated correctly and synthesize too. I wanted to write.VCD(value change dumped) file.
I got from internet few command to generate VCD file as given below:
initial begin $dumpfile ("invchn26.vcd"); // Change filename as appropriate. $dumpvars(1, t.uut); end
But have few amount of confusion:
1. The above lines will be written on the testbench. Am I right?
2. I have below files:
testbench: stimulus.v ,
the main file named F_E. it is instance by name call in stimulus file. like written as F_E call (a,b,CLK,x,y);
I wrote below lines in stimulus (testbench file) :
initial begin $dumpfile ("crt.vcd"); // Change filename as appropriate. $dumpvars(1, stimulus.call); end
But its giving error. How DO I create .VCD file with verilog and xilinx. Please suggest hints.