I am writing a VHDL code of a simple counter which receives as an input a number and that is a time in ms, and a 50 MHz clock, for example if 200 is received it has to count 200 ms so 200* 50e3 cycles, then it has to give an output named Terminal_count_end that has to remain high until a new reset signal is given (which by the way is active when '0')
I created a testbench to test it and i discovered that Terminal_count_end becomes 1 but only for one period of the clock, then it returns to 0 forever.
I am a begginer in VHDL and I really don't know what's I am doing wrong so I thank in advance anyone who can help me with this code!
The code is:
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity counter_start is generic (N : integer := 16); port (enable,clearn, Clk : in std_logic; end_time_ms : in unsigned (7 downto 0); Terminal_count_end : out std_logic); end counter_start; architecture behavior of counter_start is signal count : unsigned (N-1 downto 0); signal cifra : unsigned (3 downto 0); signal T_c : std_logic; signal T_c_end : std_logic; begin process(clk,clearn) begin if clearn = '0' then T_c <= '0'; count <= (others => '0'); elsif (Clk'event and clk = '1') then if T_c = '1' then T_c <= '0'; count <= (others => '0'); elsif (enable = '1') then count <= count + 1; if count = to_unsigned(49999, N) then T_c <= '1'; end if; end if; end if; end process; cifra_process: process(clk,clearn) begin if clearn = '0' then cifra <= "0000"; t_c_end <= '0'; elsif clk'event and clk = '1' then if (T_c = '1') then cifra <= cifra + 1; if cifra = end_time_ms-1 then cifra <= "0000"; T_c_end <= '1'; end if; end if; end if; end process; terminal_count_end <= T_c_end; end behavior;