0
\$\begingroup\$

First year EE student here, we've been learning about CMOS Inverters in class and about the of logic gates, but it hasn't really been mentioned how much this effects the design of a Circuit in industry and whether it's something that Engineers have to take account of every time they design a circuit with a gate? If it is, is this something you model using computer software before designing a board? Was just interested in some feedback on how much gate delay effects design

\$\endgroup\$
  • \$\begingroup\$ If you're flashing a LED for someone to look at ... don't worry about it. If you have to make the circuit work at a specific clock speed : worry about it. One common practice is to use an FPGA to hold all your gates. Tell the FPGA tools your clock speed and let them worry about it. (They do "static timing analysis" and tell you it's OK, or what failed). \$\endgroup\$ – Brian Drummond Apr 12 '16 at 11:48
  • \$\begingroup\$ Pick up the book called "Logical Effort", that is a good primer for relative speed between gates. You won't get into reality until later because it's complex and terrible. For a taste of reality, I see the change in driving strength vary by up to 40% on 14nm. The wire length of 30um@32nm wide on M1 is equivalent to the input capacitance of an inverter. \$\endgroup\$ – b degnan Apr 12 '16 at 12:35
1
\$\begingroup\$

Gate delay is very important! Depending on what you want to design, gate delay can be both used and something to be avoided.

Consider the JK flip flop:

enter image description here

If we keep the J & K inputs high, the Q output toggles for each rising edge of clock. The circuit does not oscillate, it toggles. Consider a starting condition where Q is high and Q-not is low. On the rising edge of clock the lower-left NAND gate's output goes low. This causes the output of the lower-right NAND gate to go high. This state is sent to the upper-left and upper-right NAND gates. For a short time both inputs of the upper-righ NAND gate are high changing its output to low and causing the RS latch inside this JK flip flop to change states. One gate delay later the output of the upper-left NAND gate goes low. But the RS latch has already changed!

There should be no change in the RS latch on the falling edge of the clock.

This process repeats its self in the opposite manner upon the next rising edge of the clock.

In this example gate delay is used to create the desired toggle feature.

Consider the common full adder:

enter image description here

This logic will sum bits A, B & a carry bit C. The output consists of a sum S and a carry bit C. To sum two 4 bit binary numbers you need to cascade 4 of these full adders using this arrangement:

enter image description here

Consider adding 0001(base 2) to 1111(base 2). The result would be 0000(base 2) with a carry. Note that only after the sum of the lest significant bit (LSB) of A0 & B0 was calculated that the LSB carry bit C1 changed to high. And upon that change the next full adder set it's carry bit C2 high. This process repeats again for the next full adder. Then again for the 4th full adder. This arrangement of full adders has a name. The ripple carry adder.

We realize that the final sum is not instantly available upon supplying the inputs to this 4 bit ripple carry adder. That we need to account for the gate delay and wait for the worst case scenario before we are able to make any decision based on the sum of the two 4 bit numbers.

In this example gate delay is avoided by waiting until the ripple carry has occurred.

\$\endgroup\$
0
\$\begingroup\$

For High frequency design, gate delay,latency,propagation delay and all these terms will be considered more.

Since switching is done at more higher frequency ie switching devices are turned ON or OFF in very short time, So here gate delay is considered and even delay in PCB trace routing will come into picture.

\$\endgroup\$
0
\$\begingroup\$

As noted, a simple circuit is probably 'don't care', within reason.

In even a simple Flip Flop, the gate delay means that there will be setup and hold times; if I were interfacing to a fast synchronous SRAM with external glue logic I would be very concerned with the timing parameters of the various gates.

Here is the read and write timing for the above device:

Fast SRAM timing

Every item on that diagram that starts with 't' is a timing relationship that must be met for the device to operate properly; such tasks are not simple and great care must be taken to ensure that any glue logic will not end causing a timing violation

As always, whether timing parameters need to be carefully considered depends on the specifics of the application.

\$\endgroup\$
0
\$\begingroup\$

In real FPGA and ASIC design gate and wire delay is critical. It's modelled with software before going anywhere near production, and the software can also have a go at adjusting gate sizes to improve delay. I used to work at a startup doing this for clock tree optimisation.

(The Logical Effort book mentioned is a good bit of theory, but when we tried to do this in practice we ended up having to do good old fashioned successive refinement, because gates are only available in discrete sizes for most logic design purposes).

\$\endgroup\$
  • \$\begingroup\$ yeah, "logical effort" is like that, but it's a good guide for new students to get intuition. The idea of "electrical effort" doing work is a nice segue into things being less idea. Reality is hilariously cruel. :/ \$\endgroup\$ – b degnan Apr 12 '16 at 17:35

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.