What would be an acceptable tolerance for length matching trace, for DDR3 SDRAM?

  • \$\begingroup\$ Would that not depend on the frequency you run it? \$\endgroup\$ – Matt Clark Apr 12 '16 at 16:26
  • \$\begingroup\$ @MattClark yep, that will determine how much you can tolerate skew-wise between say DQ/DM to the strobe. Using faster memory components with slower hosts buys you margin as well (see below). \$\endgroup\$ – Krunal Desai Apr 12 '16 at 17:22

The best answer will be from the hardware layout guide from your SoC/FPGA/ASIC vendor, especially because you will need to consider the inner-package flight times as well, which the manufacturer will give you in a datasheet / layout guide somewhere, based on your particular package (flip-chip, wire-bond, etc.). In the abscence of such a guide (like if you are doing your own DDR3 memory to a FPGA), see if their external memory interface handbook gives some ballpark numbers, or pick numbers from a vendor who provides good, conservative layout guides (IIRC, Intel used to do this).

Generally, tolerances will be the tightest within the pair (P/N), if differential, followed by intra-group tolerances (i.e. within an address group, command group, strobe, etc.). This is more applicable to PCIe, but a good practice I do is take the tolerance given by the manufacturer and half it (if practical) -- I.E. if they say match to within 0.254mm, I match to within 0.127mm. For something like PCIe where you have add-in cards that plug into another system, you're budgeting against the engineer on the other side of the system using up all of the specified tolerance.

Remember that the tolerances differ on the type of DDR3 signal it is, as well as your expected operating frequency. Choosing faster memory parts and running them at a lower frequency can buy you margin in layout -- see below examples from the Zynq-7000 PCB design guide (this is one very specific example, do not take these as gospel): enter image description here enter image description here

For this example, they also discuss needing to make your clock lines greater than or equal too the length of DQS.

A final tip: I use an Excel spreadsheet with all the requirements for the layout guide input into the sheet. I then export (via script) the lengths of every net from my PCB design document to a text file, import that into Excel, and use simple VLOOKUP to snag the net names + lengths and conditionally format based on whether they are passing or failing. This is the place to put all relevant data -- the requirements, intra-package delays, etc:

enter image description here

  • \$\begingroup\$ Clock line routed longer than the DQS line is a general DDR3 requirement. The DQS signal edge must reliably arrive to the DRAM before the clock edge if you want the write leveling feature to work. Some controllers implement features to delay the clock by register setting instead. \$\endgroup\$ – Timmy Brolin Apr 5 '19 at 23:14

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