SOLVED!!! I'll leeave the questions, see below for the solution.
In a VHDL project, I want to initialized an array that have a certain dimension, and I want this dimension is derived by a function. Here is a minimal implementation that show what I want to do:
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use work.arrayout_type.all; entity minimal is Port ( a : in std_logic; b : out std_logic ); end minimal; architecture Behavioral of minimal is variable dimension : integer; dimension := calc_adder_length(M); type array_intern is array (dimension-1 downto 0) of std_logic_vector(M+N-1 downto 0); begin end Behavioral;
Here is the package (I edited the message and I included the two separate package in a unique package) :
library IEEE; use IEEE.STD_LOGIC_1164.ALL; package arrayout_type is constant N : integer := 8; -- first member is N bit long constant M : integer :=4; -- second member is M bit long -- declaration of a TYPE of an array of M element, each element is a signal that is the output of the M shifters and the M-1 adders type array_out is array (M-1 downto 0) of std_logic_vector(M+N-1 downto 0); end arrayout_type; package body arrayout_type is -- calcluate the number of internal signal for the adders. Function body. function calc_adder_length (x : integer) return integer is variable number : integer; variable accumulator : integer; begin number := x; accumulator :=x; while(number > 1) loop if(number mod 2 /= 0) then number := number/2+1; else number := number/2; end if; accumulator := accumulator + number; end loop; accumulator := accumulator +1; -- finalization. return accumulator; end calc_adder_length; end arrayout_type;
The problem is, of course, that I cannot call the program in the architecture body before the "begin". But at the same time I cannot declare the array_intern in the architeture after the "begin". So I don't know how to do.