# Uart Full Duplex vs Half Duplex

When uC1 wants to talk to uC2 via uart, the Tx of uC1 is connected to Rx of uC2 and vice versa. Half Duplex states that only 1 uC can use the communication line at a time and Full Duplex states that both uC can use the line at the same time. The Tx and Rx pin connections still remain the same for both methods of duplexing, but how 2 different scenarios are possible? Does the presence of separate Buffers for tx and rx determine duplexing or are special IC's and pin connections needed? Im confused because im working on a system where 2 uC's communicate with each other and both can send data at any point of time across a common uart connected to both of them(uC1=UART1,uC2=UART1).This will help me decide if priority among the 2 uC's is needed or not(i.e force them to work in half duplex, cos il be using ACK/NACK for messages sent via uart,and if both can send at any point of time,theres chances of misinterpretation/corruption of data(i.e uC1 is expecting ACK from uC2 in its rx buffer but uC2 is sending a message and not an ACK for the received message)).

Update

Im using 2 LPC1778,where the UART1 TX of uC1 is connected to UART1 RX of uC2 and UART1 RX of uC1 is connected to UART1 TX of uC2. Both uC can send data at any point of time simultaneously(full duplex)and no transceivers will be used(direct uC-uC communication).The uC's have separate Tx and Rx Shift registers. When uC1 is Tx'ng,data is going to uC2 Rx FIFO. If uC2 transmits,data will be going to uC1 Rx FIFO. So, if both uC's send, there wont be any collision right?

Simplex, half duplex and full duplex shown below: -

Half duplex may make use of separate transmit_left and transmit_right wires or use some kind of hardware to permit non-simultaneous left or right transmissions on one shared wire (plus ground).

Full duplex can look like half duplex in terms of wires but, the hardware at both ends can handle simultaneous transmission and reception.

• Half duplex may use two wires just like full duplex OR it may use 1 wire with a hardware switch that controls direction at both ends. Apr 13, 2016 at 10:34
• If using two wires and transmissions can't occur simultaneously or overlap then transmission is half duplex. Apr 13, 2016 at 10:43
• To be half duplex simultaneous transmissions or overlaps "can't" happen else it becomes full-duplex (in part). It's semantics really. Apr 13, 2016 at 12:19
• I'm losing the will to live on this one.... which scenario? Apr 13, 2016 at 14:19
• If the transmission occur simultaneously or overlap it is full duplex. Apr 14, 2016 at 10:39

For electrical signaling, count the number of wires - and subtract one for the ground wire. How many are left?

You started talking about 2-wire system: one from tx1 to rx2, another from tx2 back to rx1. This is a standard Full Duplex setup.

The other option has a single wire: half duplex. If the single wire is hooked up to tx1, the other end HAS TO connect to rx2 or you'll lose data. Similarly, if the single wire is on rx1 the other end HAS TO know to switch the wire over to Tx2 (and send back data)

Full duplex is faster and simpler, but needs more wires. Half duplex uses less wires, BUT you need a protocol at each end to know when to switch betweeen sending and receiving.

For more detail, you may want to look up "collision detection" on networks. It's a protocol to sort out who talks, and who listens. Another protocol is "token passing" on ring networks.

Update I'm reading your section about hooking up 2 uC chips. Yes, these chips should be able to operate in full duplex. However...

You are sending data, both ways, AND expecting ACK/NACK responses. We are right back to protocol handling, like HDLC or DDCMP. You need to send data in some form of "packet". Each packet contains a reference number.

Example: uC1 sends packet #101, then #102, then #103. At the same time, uC2 is sending packets #201, then #202, etc.

After sending packet #103, the control setup on uC1 starts looking at the packets from uC2, checking for a "#101 ACK/NACK". If it can't see that message, eventually the system will assume packet #101 was never received - and sends packet #101 again.

If uC2 manages to send back a #101 ACK, then uC1 knows to continue on by sending packet #104 (while also looking for #102 ACK/NACK).

• so Full duplex uses 2 wires & half duplex uses 1 wire. For half duplex,the uC must use a switch to interchange connections in order for both to be able to use that 1 line? Apr 13, 2016 at 10:29
• Yes you need a switch. You also need to know when to use it. If tx1 sends an "end of message" signal, uC2 needs to see that AND flick the interchange switch. Also, uC1 needs to flick its own switch (from tx1 to rx1) after sending the "end of message". Apr 13, 2016 at 10:51
• ur answer seems to point out that the scenario i have posed is full duplex because i dont use switches Apr 18, 2016 at 5:23

Usually Transmitter and Receiver blocks on a uC are designed to be working independently. I don't know what kind of full duplex comm you are talking about. If that is regarding the user/software level implementation, the user program has to mask it's tx or wait for the reception to be completed. Else there should be some Mode (Full duplex) in uC to do this automatically, i.e., the uC will send your data after reception even though you trigger tx while reception is going on.

Hope this made you understand the concept. The next time anyone asks this kind of Question, I should find the Architecture (8051/Arm/PIC)? in the Question...

There won't be any collision