Help to translate jitter design constraint in a frequency synthesizer design with 4046 and 4017 ICs

I'm trying to design a frequency synthesizer with the old-school 4046 and 4017 ICs, with a scaling factor N = 1,5,7,10.

The input signal is a square wave with adjustable frequency from 1 kHz to 10 kHz.

I want to get a time jitter < 1% of the period.

I'm a newbie in PLL design, so I've done the only possible thing: study. I already knew control theory, filters, loop gain, stability and so on but I still can't understand where to start in the design to achieve the desired performance. Many books state that the design should start from the closed-loop bandwidth, but how do I relate this to jitter? I've read about calculating RMS time jitter from phase noise, but the datasheet of the 4046 has no data about VCO phase noise (for example) and I have zero info about the source phase noise (the project is for college and the professor didn't give me any other information).

Please if you could help me, I literally have zero ideas on how to go on.

• Control theory and your component specs will give you the phase noise in dBc/sqrt(Hz). You'll then need to decide what offset band is important to you, and integrate the phase noise to get the phase in time units. The best way is to use (or write) some software to do the calculations, then adjust the inputs until you get the performance you want. Apr 13, 2016 at 19:06
• The 4046 which is featured in www.badbeetles.com has an RC VCO .There is not a spec for phase noise on any data sheet that I have seen.You could improvise by guestimating noise on pin 6 and pin 7.This amplitude noise will yeild phase noise on pin 4.Phase noise will give you your jitter.In other words the VCO has some AM to PM conversion. Apr 13, 2016 at 20:41

I will define jitter specifically as the cycle to cycle jitter, so the time variation from one cycle to the next compared to a perfect cycle period. This is a common jitter definition and will allow me to explain the relationship between that and phase noise.

Note that a cycle to cycle jitter measurement is a delay and subtract to a phase noise or equivalently a time measurement process. You compare the time in one edge to the time in the previous edge and subtract to get the cycle to cycle jitter. Also note that time is related to phase as follows:

$$T_e = \phi_e\frac{T_p}{2\pi}$$

Where

$$T_e = \text{time error in seconds}$$

$$\phi_e = \text{phase error in radians}$$

$$T_p = \text{cycle time of one clock period}$$

A delay and substract process is a first order highpass filter with a corner at 1/T where T is the length of the delay in seconds. You can intuitively see this if you consider the lower and higher frequency offsets for phase noise. The lowest frequency offsets represent phase fluctuations vs time that are moving very slowly, so slowly in fact that after our finite delay of one cycle, the fluctuation has not changed (therefore same error in the next cycle); when we subtract to measure the cycle to cycle jitter the error will be zero. Faster fluctuations however will be uncorrelated, and so in fact will double in rms value consistent with adding (or subtracting) equal and uncorrelated noise sources.

This is shown in the figure below, and this high pass filter is effectively what is applied to the phase noise power spectral density in the process of measuring cycle to cycle jitter. Thus if you take the single-sided phase noise power spectral density $S_{\phi}(f)$, apply this effective single pole filter (along with the +3 dB factor!) and then integrate the resulting power spectral density, you will get a resulting variance. The square root of this variance after converting to time error using the first formula I gave will equal your rms cycle to cycle jitter!

Mathematically everything I described would be as follows:

$$\tau_{rms}=\frac{T_p}{2\pi} \sqrt{2\int_{f_L}^{f_H} S_\phi(f)\left(\frac{1}{s+\frac{1}{T}} \right)^2 df}$$

Where in practical applciations $f_L$ is typically 2 decades less than the corner frequency set by 1/T and $f_H$ is the measurement bandwidth of the system.

• Wow, thanks! I had lost any hope that someone would have answered to this. Do you have any reference on the subject? I've noticed a disappointing lack of (clear) resources about jitter modeling Mar 22, 2017 at 18:29
• What I showed you I had come up with on my own and confirmed with lab measurements to match up, but there could be residual flaws. Here are some other references I have collected on jitter that may help you: "Jitter Analysis: The dual-Dirac model, RJ/DJ and Q-scale", Ramson Stephens, Agilent Technologies. "Understanding Total Jitter Measurements at Low Probabilities", Stephen Didde, Agilent Technologies (Saved from Agilent Measurement Journal unfortunately with no date). "Little Known Characteristics of Phase Noise, by Paul Smith, RF Design March 2004 (www.rfdesign.com). Mar 22, 2017 at 19:13
• "Predict Phase-Noise Effects in Digital Communications SYstems" Mark Kolber, Microwaves and RF, September 1999 Mar 22, 2017 at 19:14
• In my own test on a 67 MHz PLL I measured the phase noise with a spectrum analyzer, and then provided the "phase noise cancellation" as described above due to a cycle to cylce measurement, integrated the result and converted to time to get 16.9 ps jitter. I measured the same with a Lecroy scope (that had a jitter noise floor of 2ps) and measured 17.8 ps. Accounting for the 2ps noise floor, predicted was therefore 17.0ps and measured 17.8ps. Not bad! Mar 22, 2017 at 19:20
• Looking at my notes then, what I did specifically was determine rho from an approximation of the correlation of two signals delayed in time using $$\rho = \frac{1}{1+(4*\pi f T)^2}$$ then used a cancellation ratio defined as $$1-\rho$$ which is the amount that the measured phase noise on the spec an is removed from the measurement of jitter in a cycle to cycle time domain measurement. Then I added an additional 3dB to account for the noise summation as described above. I had also put in parenthesis that I need to confirm the correlation relationship but the results came out very good! Mar 22, 2017 at 19:22