# about Synplify VHDL (code imported from Xilinx ISE)

Good day,

Need some help. Start to work with Synopsys Synplify. Import my Xilinx ISE project (fully work).

Try to run and receive - "No matching overload for to_integer" for this line

rgb(7 downto 0) <= color_lut(result_reg(to_integer(unsigned(x(2 downto 0))-1 )));


What can I do to adopt this piece for Synplify?

Just a guess: did You include numeric_std? Also Your code line seems to be wrong, because there are 5 opening ( and only 4 closing ) and no closing ;. You can try to_unsigned() later.

• Yes, numeric_std included. >code line seems to be wrong - "copy pust bug" :) brackets are correct – fpgaiua Nov 28 '11 at 18:03
• copy more correct code then :) – Socrates Nov 29 '11 at 6:37

Does it compile in a simulator? You often get more useful error message, and you should always simulate before synthesising. EDIT: Your comments indicate you have and it's fine.

XST is not always a good representation of correctness of code - it's VHDL is sometimes a little off-spec in interpretation.

I'd have thought you want something like this (with lots of extra whitespace for clarity of answer, I'd not usually write it like this in source-code). You never know, Synplify might be happier with this version:

rgb(7 downto 0) <=
color_lut(
result_reg(
to_integer(
unsigned(
x(2 downto 0)
) --close "unsigned"
) -- extra bracket here - you now have a signed integer you can subtract '1' from
-1
) -- close result_reg index
); -- close colour_lut index


Otherwise, please give more details on the data types involved.

• is that a copy/paste error? -- yes – fpgaiua Nov 28 '11 at 18:03
• >you should always simulate before synthesising -- yes, but in simulator (or after XST synthes) it's all right. – fpgaiua Nov 28 '11 at 18:22
• Can you post more code then - what type are color_lut, result_reg and x? – Martin Thompson Nov 28 '11 at 19:50