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here's my schematic.

enter image description here

I've got this circuit hooked up to those pins. Q1 is P-channel MOSFET (AO3401A), I've also got an ATmega328P not pictured, and POWER_BUTTON is connected to PC4 of the ATmega328P, POWER_HOLD_UP is connected to PC5 of the ATmega328P, VBAT_SWITCHED is connected the input of a linear voltage regulator (NCP603SN280T1G) and a 10uF capacitor. I expected in the default state that this circuit would pull the transistor gate (i.e. both POWER_BUTTON and POWER_HOLD_UP nets) up to VBAT, but as you can probably guess that's not what I'm observing through measurement.

With everything in circuit, and VBAT = 4.84V, I measure 0V at the POWER_HOLD_UP net, 3.37V at the POWER_BUTTON net. The regulator is on and regulating (not what I expected, but predictable based on the measured voltages).

With the FET removed from the board, I get 1.41V at the POWER_HOLD_UP net, and 1.49V at the POWER_BUTTON net. The regulator is not regulating (as I would expect), measured output is however 0.9V, despite there being no clear path between VBAT and the input to it.

With the FET removed from the board, and the source-drain junction bypassed with a 0-ohm resistor, I get 0V at the POWER_HOLD_UP net, and 1.2V at the POWER_BUTTON net. The regulator is on and regulating (as I would expect it to).

This last test is perhaps the most telling and most puzzling to me, leading directly back to to wonder if this is somehow related to input impedance of the microcontroller pins when they are configured as inputs with internal pull-ups disabled, but I'm grasping.

Anyone got any theories about why both POWER_BUTTON and POWER_HOLD_UP are not at VBAT in this scenario?

I was thinking about knocking those two resistors down to 3.3k and 1.0k respectively, as well as trying to lift PC4 and PC5 pins off the board and retaking measurements, but I figured I'd see what people here thought first. I've spent some time chatting with an FAE from the FET manufacturer, and I'm pretty convinced at this point that's not where my problem is originating (again based on the last experiment).

I know there are imperfections in the circuit, and I'm more than happy to try bodging fixes in. I've thought about putting in a bleeder resister (like 10k) to GND on the VBAT_SWITCHED net for example, but that had no impact. I'm just about out of inspiration, hopefully I can acquire some here.

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  • \$\begingroup\$ When your micro is not powered, its inputs are not floating. Expect them to behave as if there is a diode from each pin to the micro's Vcc supply. \$\endgroup\$ – brhans Apr 14 '16 at 19:31
  • \$\begingroup\$ @brhans, oh that's interesting, and now that you mention it I'm reminded... you see what i'm trying to do though, right? how might i do it differently? I want no current to flow into "into the system" until POWER_BUTTON is forced low (e.g. by a button), and while the system is on, I want the microcontroller to keep it on by asserting POWER_HOLD_UP low, and be able to sample the POWER_BUTTON as an ADC input to tell when the button is being depressed. \$\endgroup\$ – vicatcu Apr 14 '16 at 19:44
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    \$\begingroup\$ Use a transistor (NPN or N-channel MOSFET) to switch the gate of the P-channel rather than using the port pin directly. \$\endgroup\$ – Spehro Pefhany Apr 14 '16 at 20:09
  • \$\begingroup\$ @SpehroPefhany that makes a heck of a lot of sense. I'll have to experiment to verify, but I think I have a handle on the problem. If you guys care to submit answers I'll gladly up-vote them and accept one for completeness. \$\endgroup\$ – vicatcu Apr 14 '16 at 20:26
  • \$\begingroup\$ Actually @SpehroPefhany that only addresses how to handle POWER_HOLD_UP, but it's a clue as to how to handle POWER_BUTTON, I'm thinking something like a pass-gate in series with the microcontroller input, enabled by the POWER_HOLD_UP net would probably do the trick \$\endgroup\$ – vicatcu Apr 14 '16 at 20:35
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When switching high-side power using a p-channel FET, I always drive a small N-channel FET to attach to the pull-up, I'm not experienced with your particular processor, but Microchip processors don't do a good job of driving the outputs up to the positive rail especially if the signal has other stuff on the line. They do however go low enough to turn off the N-channel FET which will insure that your gate goes all the way to the positive rail. Note that this will invert your logic.See attached from a schematic. It also has the advantage of allowing switching of different voltages and is turned off when the processor output is low during startup.

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