I would understand the behavior of the V_C potential in this circuit. The IN-M voltage is a pulse wave with 5% duty cycle. I think that it works in this way:
- When the IN-M is HIGH the NAND 1's output is LOW so no matter how the NAND 3's output is, the NAND 2 output is HIGH.
- At this point the charging of capacitor C1 starts and V_C potential is initially HIGH and than it decreases exponentially.
- When the IN-M voltage becomes LOW and NAND 1's output is HIGH it happens that NAND 2's output is HIGH untill V_C potential goes below a treshold and consequently NAND 3's output becomes HIGH.
- At this point the V_C potential becomes LOW (because there is a negative charge on the "right" plate of the capacitor) and the discharging of capacitor C1 starts at first through the diode D1 and than through the resistor R1.
I posted a screenshot of the oscilloscope with V_C and V_in traces. The zero potential level is indicated by the arrows.
I can't understand why the V_C potential during the discharging of the capacitor tends to a potential level different from zero as if asymptotically there was a current flowing through the resistor R1.