Monostable multivibrator

enter image description here

I would understand the behavior of the V_C potential in this circuit. The IN-M voltage is a pulse wave with 5% duty cycle. I think that it works in this way:

  • When the IN-M is HIGH the NAND 1's output is LOW so no matter how the NAND 3's output is, the NAND 2 output is HIGH.
  • At this point the charging of capacitor C1 starts and V_C potential is initially HIGH and than it decreases exponentially.
  • When the IN-M voltage becomes LOW and NAND 1's output is HIGH it happens that NAND 2's output is HIGH untill V_C potential goes below a treshold and consequently NAND 3's output becomes HIGH.
  • At this point the V_C potential becomes LOW (because there is a negative charge on the "right" plate of the capacitor) and the discharging of capacitor C1 starts at first through the diode D1 and than through the resistor R1.

I posted a screenshot of the oscilloscope with V_C and V_in traces. The zero potential level is indicated by the arrows.

I can't understand why the V_C potential during the discharging of the capacitor tends to a potential level different from zero as if asymptotically there was a current flowing through the resistor R1.


1 Answer 1


When analysing operation of circuits like these I find it useful to think that the voltage across the capacitor remains constant in the very short term.

  • With this in mind, when the left side of the capacitor rises suddenly by 3.3 V (if I read your scope trace correctly) the right side rises by almost the same amount.
  • The left side is held at 3.3 V by the NAND gate. The right side is now at about 3 V (there are always some losses) has a path to ground through R1 so the voltage decays with the characteristic RC decay curve.
  • The NAND gate then switches low before the right side of the capacitor has fully discharged* and Vc is about 1.5 V. Since the left side falls suddenly by 3.3 V the right side will try to fall from 1.5 V to -1.8 V (1.5 - 3.3).
  • D1 clamps the right side of the capacitor at about -0.6 V and quickly provides current to prevent the capacitor going below this level.
  • We then see a decay from -0.6 V to zero as the remainder of the charge leaks away through the diode. Note that the curve doesn't quite look like a standard RC decay curve. It starts off very steeply just after the falling edge but flattens out a bit too quickly. This is due to the non-linear V-I curve of the diode which means that its "resistance" is increasing as the voltage decays.

* Technically the capacitor is charging at this point as the voltage across it is increasing.

I hope I've addressed the point of confusion adequately. Please ask for clarification in the comments, if required.

  • \$\begingroup\$ Thank you for your help. In the last point of your answer you said "We then see a decay from -0.6 V to zero " but actually the V_c voltage does not tend to zero . \$\endgroup\$
    – gilgamesht
    Commented Apr 15, 2016 at 6:29

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