I write a VHDL code for an adder tree, with a parametrized number of vector. It's only for Learning purpouse, so I dind't implemented the carry between the block, I simple created a larger bus so I haven't theme.
I created the internal signal adders_intern, and I created the shown algorithm. To explain it, I attach the immage with the adder tree (sorry for the quality).
Each number represent a signal in the adders_intern vector. So, in the example of the image, related to the algorithm, in the first stage the number of signal is odd so I do I(6) = I(0)+I(1), I(7)=I(2)+I(3) etc. In the second stage I do I(9) = I(6)+I(7), but in this case the number of signals is odd so the last signal is ported as is, so I(10 = I(8), and then I go to the next stage.
This bheavior is generalized for a number of signals equal to M. I check many times the algorithm, it seems correct, but the RTL add only the first two signals, and I don't know why. Here is the code (only the process) :
process (shifter_out)
variable x,f,k : integer ;
begin
for i in 0 to M-1 loop
adders_intern(i) <= shifter_out(i);
end loop;
x := M;
k :=0;
while ( (x-k)/2 > 0) loop
if ( (x-k) mod 2 = 0) then -- even case
for i in x to x+((x-k)/2)-1 loop
adders_intern(i) <=std_logic_vector( to_unsigned( ( to_integer(unsigned( adders_intern(k))) + to_integer(unsigned(adders_intern(k+1))) ), (M+N) ) );
k :=k+2;
f:=i;
end loop;
k := k+2;
x :=f+1; -- next value of x
else -- odd case
for i in x to x+((x-k)/2)-1 loop
adders_intern(i) <=std_logic_vector( to_unsigned( ( to_integer(unsigned( adders_intern(k))) + to_integer(unsigned(adders_intern(k+1))) ), (M+N) ) );
k :=k+2;
f:=i;
end loop;
adders_intern(f+1) <= adders_intern(k); -- finalization, for the odd case.
x := f+2;
k := k+1;
end if;
end loop;
outp <= adders_intern(f-1); -- the last sum is stored in the output
end process;
I'm wrong something in the algorithm, or VHDL don't permit the description of this type of sctructure trough a process?
EDIT : I understand that it can't be made by a process, because process describe the bheavior, not how the interconnections should be wired. But now I was wondering if it is possible to do it with the "generate" statements. I see some paper on the internet that use "generate", with nested for statements, to do the inverse of the tree that I want to make (from one element to multiple elements, balanced tree. I want to make: from multiple elements to one element). So I tried to do it with generate and some variable, used in the same way of the code I used in the process. But of course I got errors because I can't use variables outside the processes. I tried also to find out a clever way to manipulate the index and achieve the gol, but nothing seems to work.