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I have a board with a +5V trace from a current sense resistor across a noisy +5V plane to an OpAmp, so I thought I'd shave that particular yak soon and create a few symbols for KiCad that actually behave as expected.

How would I express in a schematic the constraint to connect this trace only to a specific pad on a specific component, even if the same net is available nearer?

I'm interested mainly in the graphical representation, because from a program logic POV it is easy to implement (separate net from ratsnest POV, same net from DRC POV), but I'd like to have a readable schematic as well.

Similarly, is there a standard for denoting decoupling capacitors and their mapping to IC pins (same problem class, basically)?

Obviously, if there are multiple standards (US, Europe, Russia) I'd like to know about that as well.

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This is tricky, but one common solution in EDA packages is net ties. These are essentially "dummy" components that act to do what you want. They tie the nets together to allow you to name them differently, and then you create some kind of PCB component to represent the copper connection. That is also one of the reasons I don't like doing net ties -- creating those custom components is a pain in the ass, IMO. I always ended up creating one specific footprint per connection on a PCB.

Here is what I often do instead of net ties:

  1. 0 ohm jumper resistors, or ferrite beads. Usually done on power rails where I might need to filter in the future, or I want to do current measurement. Cheap, easy, and simple with small impact.
  2. I do this more on GNDs, but I'll use the same GND net name with different symbols, i.e. bars and an arrow. I do this on SMPS controller ICs that have a small-signal GND and a power GND. This acts as a hint to keep the small-signal GND path separate from power GND. A note is also helpful in this case.

Granted, I do not currently work on high-volume consumer goods, so the BOM impact of a 1005 or 1608 0R resistor doesn't even cross my mind -- they're basically free for me. And if you run into some noise problems down the line, you've got a spot to toss a ferrite in and potentially easily solve your problem (perhaps add pads for extra caps in this case).

Regarding the decoupling capacitors, I simply place the capacitors intended for a specific component on the same page as that part, or the sub-symbol that contains all the power-related pins. I don't necessarily draw the direct connection between the caps and pins -- I.E. I'll tie the part to a global power symbol 'VDD_3.3' and the caps also to the same symbol. In the case of an exotic component that demands certain values connected to certain pins, I'll draw that specifically and add a note.

I believe the above is the cleanest and most expedient way to do decoupling capacitor placement on a schematic -- if you're tossing over the fence so to speak to the layout guy, a note indicating placement or a link to the layout guide is helpful.

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  • \$\begingroup\$ I like the idea of basically having net ties look like wires with the net names next to them, that would work. I've also seen 45 degree angle wires to communicate that certain traces need to meet at a certain point -- my question is whether these are sufficiently standardized that I could offer them as a "tool" and make them affect layout. \$\endgroup\$ – Simon Richter Apr 19 '16 at 2:21

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