This is my circuit. An MCU gpio pin should control the power of another IC. Because the component requires more current than the gpio pin can drive, an N-Channel MOSFET is used. This is IC has no ENABLE/SHUTDOWN/RESET pin. VCC may be different from MCU VCC. However in this configuration a virtual ground for that component is created because of the RDS_ON resistance of the MOSFET that causes a voltage drop.

A certain number of question arises:

  1. Is this a good way? Is there a better way?
  2. In order not to left components ground floating (if the MOSFET is not conducting) is this 100K pull-up resistor required or is it even allowed? Is a floating ground a problem in most situations?

Update: New circuit based on Michael's reply Unfortunately wrong.

If I understand, the circuit can even be simplified by using one logic P-Channel MOSFET like following circuit (assuming SSM3J328R P-Channel MOSFET):

P-Channel MOSFET based only circuit

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    \$\begingroup\$ The circuit that you added to your posting has been "simplified" to non-working for most cases. Few supposed logic level FETs will work for 6A with a gate drive of 3.3V. Even the FET you picked out should have a gate drive over 4.5V at that type of current level to get lowest RdsON and lower internal power dissipation. Gate drive is negative relative to the VCC for the load. So for this example the minimum VCC will have to be ~4.5V. And when the VCC is 15V you still need the level translation stage I showed to allow the P-FET to be turned on and off. So follow the suggestions made. \$\endgroup\$ Apr 21, 2016 at 10:40

1 Answer 1


The way that you propose is not a good way to switch the power to the load. You should instead switch the VCC power side and keep all the GNDs common between the MCU and the power switched device.

The technique used to achieve this would be to use a P-Channel MOSFET for the power switch and then an additional small signal transistor to provide level translation from the MCU GPIO voltage levels to the Gate drive for the P-Channel MOSFET.

Here is a picture of such a design. I show using an NPN BJT for the level translator but a small signal N-FET could be used as well as long as the gate level threshold is compatible with the MCU GPIO levels.

enter image description here

Note that there are some situations where you could be switching power to a load device and it would be desirable to keep the MCU GND separate from the switched load. This may be the case if the load generates a lot of noise, huge current surges or is a dangerous voltage such as AC mains. In this instance the load switching would be done through a relay or an opto-isolator.

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    \$\begingroup\$ This circuit also has the advantage that when the MCU powers up the switched load is off. \$\endgroup\$ Apr 21, 2016 at 10:09
  • \$\begingroup\$ It seems that I didn't understand every details. Can you explain in more detail your circuit again? Say MCU GPIO voltage is between 0 and 3.3V and VCC for load is 15V. Say, the P-FET V_GSth = 2.5V (I_DS 6A @V_GS 3.3V and V_DS 15V). What is the expected voltage required either to conduct and not to conduct the P-FET? WOULD it be possible to omit the BJT and if yes what are the requirements for that? \$\endgroup\$
    – bkausbk
    Apr 21, 2016 at 11:18
  • \$\begingroup\$ @bkausbk - The circuit is straightforward. Rather than try going into a long winded educational dialog here I would encourage putting the circuit into a simulator and running it to see how it works. The folks at Linear Technology (www.linear.com) offer a circuit simulator that is free for download. I use this all the time to characterize circuits before I build them. \$\endgroup\$ Apr 21, 2016 at 21:28
  • \$\begingroup\$ @MichaelKaras - Ok thanks anyway. I know LTSpice, however simulating such circuits with general parts mostly results in no usable answers. Let me precise my core question: Under what condition is it possible to omit the BJT and using only one P-FET? (Assuming logic P-FET). \$\endgroup\$
    – bkausbk
    Apr 22, 2016 at 8:22
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    \$\begingroup\$ @bkausbk: basically if the Vccs are the same, but you are saying they are not. P-channels require a gate driver capable of producing a voltage close to the source voltage to fully turn off. That's the purpose of R1, and Q1 is there to pull the gate potential back to ground whenever the GPIO is high, to turn on the MOSFET. There is no way around that. \$\endgroup\$ Apr 22, 2016 at 9:32

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