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In datasheets of chips, usually they have reference designs and to those designs bypass capacitors are predetermined. But, when I examine some high level designs of those chips I see different bypass capacitors. For example, if the bypass capacitor in the reference design is shown as 1 uF only, I see 0.1 uF, 1 uF and 15 uF capacitorsin a specific application circuit of that chip. So in mixed-signal designs, the designer takes extra cares for bypass capacitors.

I want to know the calculation of the capacitance values and which type of capacitor I should use in each specific application, power range and frequency range. To make this question more clear, I draw this example mixed-signal system below:

Mixed-Signal System

There are digital blocks, analog blocks an an RF block in the system. To make a case, let say there are two digital chips work in 400 MHz and 200MHz and draws 100 mA and 50 mA drain pulses sequentially. And in analog blocks, there is an ADC which processes very sensitive signal(let say about a few nV's) in 10 - 50 MHz range. Other Analog block is also can be considered sensitive and works in 5 - 20 KHz(Acoustic) frequency range. Then there is a RF block which transmits 1GHz, 20 dBm carrier waves. So, if we also add MCU to the system, how should we calculate the bypass capacitors and how to choose capacitor types as well. Please make your case with calculations and reasons. please be deterministic rather than empirical.

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    \$\begingroup\$ This is a very broad question, and there are some empirical rules of thumb; the physical separation of the functions is a key issue as well. \$\endgroup\$ – Peter Smith Apr 19 '16 at 11:10
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    \$\begingroup\$ Bypass capacitors are the easy bit, once you have grounding, routing and supply filtering sorted out. \$\endgroup\$ – Neil_UK Apr 19 '16 at 11:13
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It depends. There are no universal calculations to answer your question. Well, except for SMPS circuits where the core functionality is voltage ripple and ripple currents are significant.

One way of viewing the power plane is as a power net impedance, trying to minimize the impedance allowing best possible reaction time from the components with minimum ground bounce. The other approach is to see power plane as a bucket of electrons that should not wobble too much with switching circuitry.

These approaches are not mutually exclusive as large caps reduce voltage ripple and small caps are good for high frequency impedance.

One very important thing to remember when you connect different size capacitors in paraller is that this creates unexpected impedance spikes. So in general you have to be careful not to create a high-impedance zone on a circuit load frequency.

Most people just plop 100nF bypass cap on each power pin and add a larger (10uF or similar) cap farther away from a major component such as FPGA or a high-speed ADC. For high-speed circuits you may want to use a tool such as murata simsurfing to pick a specific capacitor physical size/value to create an resonant dip on the fundamental frequency. Note that tuning the capacitor in this way allows the circuit to switch faster which may in turn create worse EMI.

And as a final note, always connect bypass caps right up to the power pin, not five millimeters away, if at all possible. It's ideal to connect to both GND and VCC pins this way but you may stick the other end of the cap and GND pin to GND plane with a via as necessary. Having the bypass caps on the other side of the PCB degrades performance as there's the additional via inductance but this becomes signifant only with increasing frequencies.

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