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There is a cascode amplifier seen on the picture below. A rectangular pulse with amplitude of 10 mV is sent to the input.

Due to large negative amplification gain of the cascode amplifier, output first decreases (at the left front of the impulse) and then increases (at the right front of the input signal).

What I cannot understand is why settling time at the right front is much larger than settling time for the left front. That is, why does transition of the output from max to min happen quickly, while transition from min to max takes a lot of time? Or in other words, why the output response to the left and right fronts of the input impulse is not symmetrical (long at the right and short at the left).

I used LTSpice for simulation. SPICE Level 3 model was used for long-channel transistors.

Several clues I found out. 1) Settling time at the right front is larger for larger load resistances. The response becomes symmetrical for smaller loads (e.g. 1 MOhm). 2) The effect is related to non-linearity of M2. The response is symmetrical for small amplitude of input signal. E.g. for an amplitude of input impulse of 1 mV, the output is symmetrical (settling times are the same). Note that M2 triodes when the output voltage is low.

Figure:1 Schematic Figure:2 Input and output response

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  • \$\begingroup\$ LTSpice model of the schematic and key transistor parameters can be found here \$\endgroup\$ – Sergei Gorbikov Apr 19 '16 at 11:52
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This is a very high-impedance circuit, and this means that parasitic effects — particularly parasitic capacitances — are going to be important.

Specifically, the upper transistor has a significant capacitance associated with its drain terminal. When the transistor turns on, it can discharge this capacitance very quickly, because the current flow to ground is essentially unlimited. However, when the transistor cuts off, you only have a fixed current source charging this capacitance.

Qualitatively, you would expect to see a linear ramp of the capacitor voltage, but in your situation, the load resistance "steals" more and more of the available current as the node voltage rises, so you end up with an exponential curve whose shape varies with the load resistance. A smaller resistance gives a shorter R-C time constant.

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  • \$\begingroup\$ Dear Dave, thanks for your help. You correctly found out the reason to be a capacitor between drain and gate in M2. Just I case, I attach the link to the pic from the simulator, where it's seen there is a gate current at M2 (Ig(M2) at the pic) during switching (yes, current through the gate). There is a peak in current when the capacitor discharges through the ground (through M1), and a relatively low current at charge phase (through current source on top). So, I think, it would be correct to treat your answer as a solution to the problem. Thank you. \$\endgroup\$ – Sergei Gorbikov Apr 19 '16 at 15:31
  • \$\begingroup\$ Maybe it could be useful for somebody. Discharging of a capacitor is indeed easy and fast: just short two plates of it with a good conductor and the capacitor will discharge fast. However, charging it is "more challenging". If current supply is limited, it will take time equal to Q/I where Q is a stored charge and I is the current supply. So, if Q is large and I is small, charging time is large. \$\endgroup\$ – Sergei Gorbikov Apr 20 '16 at 15:37

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