There is a cascode amplifier seen on the picture below. A rectangular pulse with amplitude of 10 mV is sent to the input.
Due to large negative amplification gain of the cascode amplifier, output first decreases (at the left front of the impulse) and then increases (at the right front of the input signal).
What I cannot understand is why settling time at the right front is much larger than settling time for the left front. That is, why does transition of the output from max to min happen quickly, while transition from min to max takes a lot of time? Or in other words, why the output response to the left and right fronts of the input impulse is not symmetrical (long at the right and short at the left).
I used LTSpice for simulation. SPICE Level 3 model was used for long-channel transistors.
Several clues I found out. 1) Settling time at the right front is larger for larger load resistances. The response becomes symmetrical for smaller loads (e.g. 1 MOhm). 2) The effect is related to non-linearity of M2. The response is symmetrical for small amplitude of input signal. E.g. for an amplitude of input impulse of 1 mV, the output is symmetrical (settling times are the same). Note that M2 triodes when the output voltage is low.