I am trying to design a H-bridge circuit for my project to drive a thermoelectric cooler (TEC). Basically, I am trying to control the TEC with a voltage source driven by PWM.

Now the problem is, I have a 5V DC source but my microcontroller (ESP8266) uses 3.3V logic. Since the space for components is limited, I would like to drive the MOSFET directly from the microcontroller.

I have built a circuit based on some things I have found on the internet but am not exactly sure if it is correct. The TEC I am using is expected to draw up to 1A at 1.7V (maximum); the MOSFETS I am using are ROHM RZR040P01TL (p-type) and RUR040N02TL (n-type) which are rated at 4A, have Vgs(th)~=1.3V and built-in GS protection diodes.

  1. Since I have never designed an H-bridge before, my first question would be about the design. Does it look like something that would work or I am missing something here?
  2. When I increased the PWM signal above zero, there was a high pitch noise coming from the MOSFETs. Is this something to be expected or does that signal an issue in the circuit?

I have tried sending low duty cycle PWM from the microcontroller (1-10%) which seemed to be working fine - while the MOSFETs were still buzzing, the TEC was working fine and there was around 0.4V voltage accross the terminals (which you would expect). However, when I increased the duty cycle to 20%, one of the N-type MOSFETs blew out.

I am guessing that this either happened because the MOSFET overheated or because I have done something horribly wrong in my circuit design.

I would appreciate some advice on building MOSFET H-Bridge circuits in general as well as some specific recommendations for this particular design.

Original design

Update #1:

I have redesigned the circuit to have each MOSFET switch separately as @WhatRoughBeast suggested. I also have added two N-type MOSFETs to control the P-type gates which should solve the voltage difference problem. This appears to have solved the noise issue - now buzzing only appears if I reduce the switching frequency to 5kHz or lower.

In the current configuration I am trying to control the direction and voltage by:

  • having B1 and B2 set to LOW, A2 to HIGH and PWM-controlling A1

  • having A1 and A2 set to LOW, B1 to HIGH and PWM-controlling B2

While the MOSFETs appear to be working now (as in not overheating and blowing up), it seems I have another problem - with 5V supply, whatever PWM duty cycle I use, the TEG always receives the full 4.5V (using 10-20kHz).

Re-designed circuit

  • \$\begingroup\$ First question: what are you doing with the Tec that you need current in both directions? Are you trying to both heat and cool? \$\endgroup\$
    – Mark
    Commented Apr 21, 2016 at 23:08
  • \$\begingroup\$ Second question: Do you really need those low-pass filters? Your MosFETs will not like the inductive spikes that they will cause. \$\endgroup\$
    – Mark
    Commented Apr 21, 2016 at 23:10
  • \$\begingroup\$ Third question: Have you analyzed the switching times of those MosFETs? Is there the possibility of shoot-through? That will kill-a-FET before you can say "How should I really be controlling these gates?". \$\endgroup\$
    – Mark
    Commented Apr 21, 2016 at 23:13
  • \$\begingroup\$ Hi Mark. Yes, I am building a temperature regulator that should be able to both heat and cool. Regarding the LC filter, I have seen a post on driving TECs with PWM and it was highly suggested to add a low-pass to filter the PWM signal. I guess they could be removed if I switched fast enough. There was potentially a shoot-through. However, I have redesigned it just as WhatRoughBeast suggested and now have only one gate PWM-controlled at a time. \$\endgroup\$
    – Simas V.
    Commented Apr 25, 2016 at 22:29

3 Answers 3


You must drive this kind of bridge with at least 5V (or close to- 4.7V will guarantee less than 1mA of conduction according to the datasheet).

enter image description here

As you have it, when an input to the bridge is at 3.3V, the N-channel MOSFET is 'on', but the P-channel is also pretty much on with 1.7V nominal drive, and it will typically conduct several amperes of current, which will fry it or the N-channel or both, depending.

You can use a voltage translator or a MOSFET driver. The latter will be capable of much more drive current and will result in less heating, but will cost more.

  • 1
    \$\begingroup\$ Thank you for the insight @Spehro.I somehow must have made a mistake in my calculations when looking at the specs. I have been thinking and figured that it should be possible to make use of the leftover N-type MOSFETs I have to build a 2nd layer switch. imgur.com/Ao5RcxI \$\endgroup\$
    – Simas V.
    Commented Apr 21, 2016 at 22:34

Another way to look at this is to see what happens to the transistors as the gate voltage goes from zero to 5 volts. Spehro has pointed out the appropriate rating on the data sheet.

If the voltage is less than 0.3 volts, the p-type will be on (gate-source voltage 4.7 or more) and the n-type will be off. For voltages greater than 4.7 the p-type will be off and the n-type will be on. For any voltage greater than 0.3 and less than 4.7, both transistors will be on, and one or the other is going to get very hot. This assumes, of course, that you use the minimum Vgsth. Since this is specced for 1 mA, this is very conservative, but it's pretty clear that using 1 volt will get you in trouble. The condition of both FETs being on simultaneously is call "shoot-through" for obvious reasons.

You have two possible routes to go. The first is to get a gate driver. This will transition through your danger zone very quickly, and the shoot-through will only last a few 10s of nanoseconds.

The other possibility is to stagger the timing of the two gate drives so that only one is driven on at any time. This is often built in to integrated bridges and bridge drivers. It will take a good deal more thought and effort than doing it the way you're doing it now.

  • \$\begingroup\$ The simplest way to stagger the gate voltages is to have an RCD one-directional delay circuit with a humble NAND logic. Two logic gates for positive side and one for negative side if you want to use the same PWM signal for both. \$\endgroup\$
    – Barleyman
    Commented Apr 26, 2016 at 9:23

There are alternate ways of doing this. Right now you have two sync buck circuits. You could replace this with a single buck controller which does not need to be synchronous @ 1A output. On top of that you'd need a set of mosfets which can reverse the TEC polarity. In essence one pair of N-MOSFETs which will connect + to 1.7V and - to GND. And a second pair which will connect + to GND and - to +1.7V.

This is probably easier to pull off than two separate syncbuck circuits as you only need one PWM signal and two on/off signals with open-collector NPN transistor to let the topside Mosfets have full +5V gate voltage. 1.7 + 1.3 = 3V but with 5V it's firmly in the saturation region with minimal RDS on.


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