How to get a default UCF file of the Xilinx Virtex-5
It doesn't seem to be anyhere. If I have to make it by myself, would you let me know how to generate a UCF file for a Xilinx Virtex-5 XC5VLX110?
There is no such thing as a "default UCF file" for a Xilinx part. The names and functions of pins are entirely dependent on your board design.
Use the Xilinx ISE Constraints Editor or PlanAhead to create a UCF file.
XC5V110T is for example mounted onto the Xilinx XUPV5 board. This board is equivalent to the ML505 board: same pin-out, same external devices, but a "bigger" FPGA.
Our PoC-Library ships with a set of UCF, SDC and XDC files for many common development boards, including Xilinx University Program (XUP) boards, like Atlys, ML505 or ZedBoard. See the
ucf/ folder for a full list of supported boards.
We split the master UCF file of each board into small portions. For example there is the:
Clock.SystemClock.ucf, which contains all constraints for the 200 MHz system clock (2 pins, I/O standard, timing net and timespec for 200 MHz), or the
GPIO.Button.Cursor.ucf, which contains all 5 cursor buttons.
Additionally, the folder contains some UCF files, needed for cross-clock FIFOs, synchronizers and so on. Such constraints are not covered by master UCF files.
How can these files be used?