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I have a question regarding the physical connection of an SPI bus.

I have an SPI master (a PIC32 device) and a number of slaves (in this case PIC16 devices). I'm only writing to the slaves, and the protocol takes care of which one does what when, so there are no MISO or SS signals to worry about and I'm just paralleling the data and clock lines to all slaves. The total length of the bus is no more than a couple of feet (say 60cm) and I'm running the SCK at 8MHz.

Now, the physical placement of the slave devices (which are actually interface nodes on other boards) is such that the SPI bus loops right back to the master so that it would be possible to connect both ends of each loop to MOSI and SCK respectively.

The following diagram shows what I mean - I'm talking about the red dotted connections - and the question is: is it a good thing to do this or not?

SPI bus

I have power and ground doing a similar journey, and this is obviously - and demonstrably - useful because it minimises the voltage drop caused by the slaves. However, I have no idea if it's a good or bad thing to do the same with these signal lines. Should I instead allow for some kind of termination - resistors to ground(?) - or maybe resistors in series to suppress reflections, or what?

I've tried it both with and without connecting the dots, so to speak, and there's no functional difference and no changes I can see on the 'scope, but maybe if it was a little longer than 60cm or a little faster than 8Mhz, I'd have a problem? So I'm looking for advice on what to do that will keep me out of trouble if anything changes.

Although this question is particularly troubling me for a 60cm SPI bus @ 8Mhz, are there any general principles for other situations? Maybe pull-ups on an I2c bus should be placed differently?

Any links to suitable reading material would be welcome too - I've not found anything that covers this specific question.

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  • \$\begingroup\$ I am not quite sure what problem you are trying to solve with that connection \$\endgroup\$ – PlasmaHH Apr 22 '16 at 12:40
  • \$\begingroup\$ @PlasmaHH Well, that's really my question - I don't have a problem to solve but I do have that option. I know it helps with power lines, I don't know if it helps with signal lines. Is it a stupid question? Maybe I'm overthinking. \$\endgroup\$ – Roger Rowland Apr 22 '16 at 12:43
  • \$\begingroup\$ I'd add that ideally, a 4-layer PCB and dedicated Vdd and Vss planes would be a good idea here for several reasons, along with dedicated bypass caps very close to each device. \$\endgroup\$ – rdtsc Apr 22 '16 at 13:53
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    \$\begingroup\$ IMO I would do the connection you proposed in red and get rid of the connection from slave 3 to slave 4. \$\endgroup\$ – lucas92 Apr 22 '16 at 13:55
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Loop back? NO. If the line is long enough to need termination (longer than risetime*c/10 or so), then drive it strongly enough to end terminate it properly, and match the line and termination reasonably well. If the line is short enough not to need termination, then it won't need the 'extra' conductivity that you seem to be looking for with the looped back connection.

A series resistor? NO. That style of source-end termination only works for a single point receiver at the end of the line. At earlier points on the line, you get the worst possible waveform for your receivers, which is a step to half voltage, followed by a dwell, followed by another step to full voltage.

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  • \$\begingroup\$ Ok thanks - can you explain what you mean by "drive it strongly enough"? You mean not straight from the PIC but via MOSFET or something? Also, to "terminate it properly", you mean resistors to ground? I understand the point re rise time rather than clock frequency determining the need for termination, can you show the full rule-of-thumb calculation? Rise time in what units? What's c/10? \$\endgroup\$ – Roger Rowland Apr 22 '16 at 13:20
  • \$\begingroup\$ @RogerRowland 'strongly enough' so that it develops a good logic level into the load of the termination. A uC output might be strong enough, might not, depends on the termination and its drive strength. Use a buffer, or two in parallel if it's not got enough drive current. 'Properly' means shunt resistive impedance. Whether that's to ground, or to mid rail, or AC coupled, depends on the system. If you ever 3-state the driver, then it has to be to ground to maintain valid logic levels. Otherwise termination to mid rail loads the driver less. \$\endgroup\$ – Neil_UK Apr 22 '16 at 13:24
  • \$\begingroup\$ @RogerRowland rise time in seconds, c speed of light in m/second, so risetime*c in metres, /10 is a bit handwavy for 'an insignificant fraction of the risetime present simulataneuosly on the signal line' \$\endgroup\$ – Neil_UK Apr 22 '16 at 13:26
  • \$\begingroup\$ Thanks again Neil, this is really useful! I think I would benefit by performing some experimentation to make sure what you've said sinks in - maybe a rainy weekend will be well spent. \$\endgroup\$ – Roger Rowland Apr 22 '16 at 13:32
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The problem I see with the loop topology is that it's hard to place the terminators correctly to suppress reflections. this doesn't matter much at 8MHz, but might have become an issue at higher frequencies or with longer lines.

The only case I see where the dotted lines could help is when the propagation delay from master to SLAVE 6 was unacceptable. In that case, you would connect the dotted lines, but break the loop somewhere in the middle (say, between SLAVE 3 and SLAVE 4), and terminate each branch independently.

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With fast signals or long lines, signal reflection becomes a problem. In those cases, you have to properly terminate the line by putting a resistor connecting the end of the line and ground (not the beginning of the line). The termination makes the line "look electrically infinite", so the signal doesn't come back. Termination sometimes also needs LC elements to counter reactive impedance.

However, for your case, termination is not needed (short line for you signal speed, assuming you're not operating in an electrically noisy environment). That's why you see no difference. It is also bad design practice to loop your signal. Doing so makes the signal loop, introducing noise in your circuit (and it loops in both directions). It also makes it easier to capture RF noise in your lines.

Additionally, it's usually also bad to loop ground and power lines. Digital switching noise and ground loops are there too, and they can have dramatic impact on analog circuits. If needed, you can use Y forks (no connection in the far end) to reduce voltage drop. If that's not enough, use wider traces (wider trace->less resistance->less voltage drop).

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