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I design a frequency divider in FPGA. It is nothing more than the D flip-flop, which use the inverted output as input. Then on the output of D flip-flop is signal with half-frequency of input CLK signal.

http://www.radio-electronics.com/info/circuits/logic_d-type_divider/d-type_frequency_divider.php

The problem is, that the output signal is bad. For a half-period of input signal, it is OK, but in the second half period there is a lot of impulses in output signal.

Everything goes to sufficient state when I try to measure signal in input. When I connect to input just the piece of cable, it helped too. So I think the input signal is with some noise (it has hairs or fur or how to say it) and that make this problem.

More information: Frequency of input signal is 500Hz

This input signal is generated by the device I need to use. I tried to look at this signal by oscilloscope, but I influence it by measuring. So I don't know whether the input signal is already noisy, or the noise is generated somewhere in the trace to FPGA.

There is a level-converter (sn74lvc4245apwr) connected between the source signal and FPGA, it changes voltage level from 5V to 3V3. There is a rather long trace between output of level-converter and input to FPGA. There is nothing else connected to this trace. The GND is located between every signal path on the board. The schematic of the board on which I test it is complex and therefore it is difficult to share it here.

The FPGA belongs to Darnaw Module (Enterpoint, .uk, pga-modules), which is connected to PCB by soldering (it is in a socket)

The FPGA dessign is done in HDL.

HDL code:

Port (
 CLK_IN  : in STD_LOGIC;
 CLK_OUT : out STD_LOGIC;
);

...

   process(CLK_IN)
   begin
        if falling_edge(CLK_IN) then
             CLK_OUT <= not CLK_OUT;
        end if;
   end process;

I got an advice - to connect this CLK_IN signal to another I/O pin inside FPGA and then use this new signal. Image of this workaround: http://dl.dropbox.com/u/37820110/circ.gif

This advice helps, the output of the FPGA is better. I think the signal in input improves due to I/O circuits, it has to pass through. But it consumes two more pins of FPGA, so I don't like this solution.

Is there any other solution I can do in the input of FPGA or in FPGA inside logic? I can also give something into the trace of input signal, some termination or logic gates to improve this input signal. But I cannot change the source of clock signal.

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  • \$\begingroup\$ On the level converting buffer, do you have appropriate voltages on the OEbar and DIR pins? Do you have pull-ups or pull-downs on the low-voltage side to give a known level when the buffer is tri-stated? \$\endgroup\$ – The Photon Dec 1 '11 at 16:53
  • \$\begingroup\$ Unfortunately, I can't comment on the HDL, since I only know Verilog. \$\endgroup\$ – The Photon Dec 1 '11 at 16:54
  • \$\begingroup\$ Also any change if you re-seat the FPGA module in the socket? Or re-route the output to a different output pin? A flaky socket connection on one pin could explain what you're seeing. \$\endgroup\$ – The Photon Dec 1 '11 at 17:02
  • \$\begingroup\$ @The Photon The OEbar and DIR pins are set right, which tri-stated buffer do you mean? \$\endgroup\$ – srnka Dec 2 '11 at 15:10
  • \$\begingroup\$ I mean the 'LVC4245. \$\endgroup\$ – The Photon Dec 4 '11 at 2:38
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Very difficult to say why this is happening without more information (scope picture, PCB layout, schematic etc)
What frequency is the signal? Where exactly is it coming from? (the FPGA? or discrete flip flop - not entirely clear from your question) How long is the trace from the pin? What is connected to it?

It could be that it's the way you are testing things is the problem. Have you removed the probe ground clip, wrapped a short wire round the barrel and attached this to the nearest ground point to the signal pin?
If it is really there, then it could be caused by not so great layout of the PCB. Do you have solid ground/power planes on the board? Is every power pin properly decoupled with the values recommended by the manufacturer?
If you can provide some more info it will be easier to suggest where the problem lies.

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Two ideas:

Is your FPGA design done in HDL or schematic? The point about the output being clean during half the clock cycle and noisy in the other half makes me think that if this an HDL design you might have generated a D-latch rather than a D-flip-flop.

Also, what is the source of the input clock? If it's an (P)ECL gate, have you provided the required termination? True PECL logic can only drive high, and requires a pull-down resistor on the output to provide an output low. PECL-compatible output logic from an FPGA would not have this problem, though.

As Oli mentioned, and others will also, more information will allow us to give much better answers. Complete schematics of your board and schematics or HDL for your FPGA would be a good start.

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