I design a frequency divider in FPGA. It is nothing more than the D flip-flop, which use the inverted output as input. Then on the output of D flip-flop is signal with half-frequency of input CLK signal.
The problem is, that the output signal is bad. For a half-period of input signal, it is OK, but in the second half period there is a lot of impulses in output signal.
Everything goes to sufficient state when I try to measure signal in input. When I connect to input just the piece of cable, it helped too. So I think the input signal is with some noise (it has hairs or fur or how to say it) and that make this problem.
More information: Frequency of input signal is 500Hz
This input signal is generated by the device I need to use. I tried to look at this signal by oscilloscope, but I influence it by measuring. So I don't know whether the input signal is already noisy, or the noise is generated somewhere in the trace to FPGA.
There is a level-converter (sn74lvc4245apwr) connected between the source signal and FPGA, it changes voltage level from 5V to 3V3. There is a rather long trace between output of level-converter and input to FPGA. There is nothing else connected to this trace. The GND is located between every signal path on the board. The schematic of the board on which I test it is complex and therefore it is difficult to share it here.
The FPGA belongs to Darnaw Module (Enterpoint, .uk, pga-modules), which is connected to PCB by soldering (it is in a socket)
The FPGA dessign is done in HDL.
Port ( CLK_IN : in STD_LOGIC; CLK_OUT : out STD_LOGIC; ); ... process(CLK_IN) begin if falling_edge(CLK_IN) then CLK_OUT <= not CLK_OUT; end if; end process;
I got an advice - to connect this CLK_IN signal to another I/O pin inside FPGA and then use this new signal. Image of this workaround: http://dl.dropbox.com/u/37820110/circ.gif
This advice helps, the output of the FPGA is better. I think the signal in input improves due to I/O circuits, it has to pass through. But it consumes two more pins of FPGA, so I don't like this solution.
Is there any other solution I can do in the input of FPGA or in FPGA inside logic? I can also give something into the trace of input signal, some termination or logic gates to improve this input signal. But I cannot change the source of clock signal.