My device has sinking output (Vcc=3.3V), the LED current (and voltage) is controlled by another device (a voltage controlled constant current source) as indicated at VLED. The LED IV curves (as measured) appear below. I am using both, on two different outputs. The forward current for both is 100mA. It is important to be able to maximize the LED output by allowing as close to 100mA as possible. What type of mosfet or transistor and resistor pull-ups or pull-down arrangement can I use? I have viewed many other articles but none seem to address current controlled elsewhere.

enter image description here

  • \$\begingroup\$ This is a little mixed up. Your schematic shows and external current source but still includes a series resistor. It gives IV curves for infra-red and red LEDs. Which are you using? As close to 100 mA as possible is 100 mA. What LED application is so demanding? If that's the LED absolute max rating you may need to derate. Can you edit your question to explain what you're really trying to do and what the VLED power supply really is. Otherwise you're asking us all to guess, we'll waster our time and you won't get a good answer. \$\endgroup\$ – Transistor Apr 22 '16 at 22:05

With the LED current properly controlled by the external source, all you need is something to sink up to 100mA effectively. Something like this:


simulate this circuit – Schematic created using CircuitLab

Replace Q1 with a low Vgs MOSFET if you want to waste less current through R1.

  • \$\begingroup\$ An N-Channel mosfet would not work here, right? From my understanding, for an N-channel to conduct, the gate must be higher than the source, in which case R1 would keep the Gate pulled up and the n-channel mostfet on. Wouldn't that invert the logic? For a P-channel to work, wouldn't the resistor and diode need to be on the low side? \$\endgroup\$ – JoeChiphead Apr 23 '16 at 21:51
  • \$\begingroup\$ With a N type transistor, high input to base (or gate) means on. As the way it is drawn above, the voltage range at the Open Drain Output is 0V to 3.3V. \$\endgroup\$ – rioraxe Apr 24 '16 at 1:22
  • \$\begingroup\$ If you want to put in a P type transistor, the resistor would still be on the high side if driven by an open drain output. It could be more efficient to have the LED at the bottom. The voltage range of the base (or gate) would be the maximum of External Current Source and 0V, and you would have to account for that accordingly. I don't know where the Open Drain Output is coming from, but if coming from a uC, the voltage rating would almost certainly be exceeded. \$\endgroup\$ – rioraxe Apr 24 '16 at 1:24
  • \$\begingroup\$ Each output is an open-drain current-sinking output rated at 50mA and 7V. Can you explain why P Channel configuration would exceed the devices output rating? Why would it be more efficient to have the resistor on the high side and led on the low side? It sounds like the better configuration is an end channel and live with the inverted logic? \$\endgroup\$ – JoeChiphead Apr 25 '16 at 12:19
  • \$\begingroup\$ When using a p-channel, to turn it off, the base or gate has to go as high a voltage level as the emitter/source. In this case, a pull up resistor to External Current Source would be the simplest way for turning off the transistor. That means whatever is driving the gate has to withstand the highest voltage that the External Current Source can put out. To turn on the transistor, the Open Drain Output would go to 0. If transistor is put at the bottom, the voltage level of the emitter or source cannot get lower than Vbe or Vgs. That voltage drop Vce (Vds) causes some wasted power. \$\endgroup\$ – rioraxe Apr 30 '16 at 1:15

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.