simulate this circuit – Schematic created using CircuitLab

I am working on a binary calculator using 2n3904 NPN transistors. I noticed when using a NOT gate the voltage gets divided when running the ouput of the NOT gate to a 10K resistor that controls the base pin of another transistor. Is there any way to avoid this?

  • 2
    \$\begingroup\$ We love schematics. Much better than words. There's a schematic button on the editor toolbar. It's really easy to use. Welcome to EE.SE. \$\endgroup\$
    – Transistor
    Apr 24, 2016 at 17:41
  • \$\begingroup\$ A full circuit would be usefull. This site has an integrated circuit editor which should be a dequate for this kind of circuit. \$\endgroup\$ Apr 24, 2016 at 17:41
  • \$\begingroup\$ Can I edit my post \$\endgroup\$ Apr 24, 2016 at 17:45
  • \$\begingroup\$ @user3657511 Yes, you can edit your post by clicking the "edit" text below the post. Additionally, the post editor has a built-in schematic editor which can be accessed by clicking the {} button at the top of the editor. \$\endgroup\$
    – uint128_t
    Apr 24, 2016 at 17:48

1 Answer 1


Because R4 is connected to the base of Q2 -- when Q1 is off, it forms a load on Q1's collector (R1), so the voltage there won't rise above about 6 V.

This doesn't really affect the performance of the NOT gate -- its threshold is about 0.8 V, so any input higher than this will be a '1'.

Given that the transistors have a beta (gain) of well over 50, you don't need to use 10k -- you could use (say) 100k. This would allow the '1' voltage to rise to (approximately) 9V*100k/(100k+4.7k) = 8.6 V


Your Answer

By clicking “Post Your Answer”, you agree to our terms of service and acknowledge that you have read and understand our privacy policy and code of conduct.

Not the answer you're looking for? Browse other questions tagged or ask your own question.