In integrated circuit manufacturing I came across the term "risk wafer" which seems to be different from a "normal" wafer. But I can't find any information online on what a risk wafer really is.


1 Answer 1


When you release a design to manufacturing, i.e. Tape-out, fracture (mask making) and then lot start what is normal is that you start a ES (engineering sample) lot that is smaller than a full production lot (25) the size of this ES lot is dependant upon the fab, but is typically 12 or so. You then put in wafer holds at various points in the process. You start with 12 wafers, but three get held at say implant, and then another 3 get held at gate poly etch, and then another 3 get held at metal 1 thus allowing the final 3 to go through to the end step.

This is done so that if you find problems at various steps you can correct the issues and then restart these held back wafers and not incur as long of a time delay. Also it doesn't make sense ot fab 25 wafers that go to scrap.

You can never just hold 1 wafer as a lot of processing steps do multiple wafers at a time (say 6, or 3 or 4) and thus if you stop just one wafer, it would have to have a replacement "dummy" wafer with similar processing put into it's place. Fabs don't like wasting production capacity on scrap.

The amount held at each stop will depend on the machines (3 wafers, or 4 wafers etc. at that machine center).

The "risk wafer" that you mention, can be the first lot of 3 that makes it through ES with stops or holds at various places for the other wafers in the lot. The first ones through are far "riskier". The wafers held at the various locations are maybe not so risky so they may not be considered risk wafers. Although some fabs do consider them that.

And finally in some fabs, any non-qualified wafer run are considered risk wafers.

So the term will depend upon the fab you use.

A hat tip to @bdegnan who pointed out that in some fabs, a "risk wafer" is one where a process waiver has been requested and granted. So might ask for a change in process steps, dosage, or be adding new stapes (that have yet to go through qualification) or even a DRC (design rules check) waiver. Captured this from the comments.

  • \$\begingroup\$ We get the "risk wafer" sticker when we ask for DRC and doping wavers. For instance, if you want to make a MESFET on a standard CMOS process, you end up breaking enough non-critical rules to get the flag even if you don't actually "break" any rules. \$\endgroup\$
    – b degnan
    Apr 25, 2016 at 17:07
  • \$\begingroup\$ @bdegnan you should add as a separate answer, I forgot to add that aspect. Good point! \$\endgroup\$ Apr 25, 2016 at 18:24
  • \$\begingroup\$ You pretty much hit it so I didn't think that my single errata was enough for a proper answer. \$\endgroup\$
    – b degnan
    Apr 25, 2016 at 18:27
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    \$\begingroup\$ @bdegnan edited and added to my answer, with attribution. Comments get scrubbed so salient information needs to migrate into the answer field. \$\endgroup\$ Apr 25, 2016 at 18:32
  • \$\begingroup\$ @placeholder: Could you explain, what a "non-qualified wafer run" is? \$\endgroup\$
    – Fritz
    May 19, 2016 at 15:49

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