0
\$\begingroup\$

I have bought a few ADCs from http://www.ti.com/product/ADS131E04 and I cannot get hear from them via the SPI.

I am putting the ADC in a TQFP socket and I connect the PWDN, RESET, SCLK, CS, DIN, and DOUT signals to the respective pins of an Arduino Due microcontroler (3.3V). I am also powering via DVDD and grounding via DGND. This should be enough for me to read a register so I can see that the SPI communication with the ADC is working. Unfortunately I don't hear back from the chip. The SPI read register request is sent to the ADC but the chip does not reply back. I have tried almost everything, including manually generating the SPI waveform. I am checking everything with a scope and a logic analyzer. I simply don't know how to get this working.

Edit 1: Thanks to everybody for giving suggestions. Today I have redone all wiring and I made sure that the power-up is fine. I measured VCAP1 and it gets to approx. 1.3V, so the analogue power-up is OK. I checked all CLK and SCLK requirements and they seem fine. This is a screenshot of the logic analyzer:

enter image description here

\$\endgroup\$
2
  • 1
    \$\begingroup\$ Can you share the waveforms / do you have a logic analyzer? What are you getting out from the slave device? \$\endgroup\$ Apr 26, 2016 at 6:09
  • \$\begingroup\$ The arduino has SPI options for MSB or LSB first, could that be the issue? \$\endgroup\$
    – Sam
    Apr 26, 2016 at 6:54

2 Answers 2

1
\$\begingroup\$

Are you sending an additional transfer to allow the part to send data back? The SPI protocol does not allow for the slave device to send back data without the master sending the necessary clocks. To send these clocks, you need to send another transfer. The process is like this:

  • The master selects a slave (~CS goes low).
  • The master sends a request for data to the slave (MOSI->DIN, SCLK clocks).
  • When the transfer completes, the slave decodes the request and puts the data in its transmit buffer.
  • The master sends a "dummy" byte of data to the slave (MOSI->DIN, SCLK clocks).
  • During that "dummy" transfer, the slave returns the requested data to the master (DOUT->MISO).
  • The master removes the data from its receive buffer and releases the slave (~CS goes high).

I suspect that you are missing that fourth operation.

\$\endgroup\$
3
  • 1
    \$\begingroup\$ I am sending an extra byte and clocking the slave so I can read back the result. But nothing shows-up. I will put tomorrow the screenshots. \$\endgroup\$
    – major4x
    Apr 26, 2016 at 6:32
  • \$\begingroup\$ Dang. I will look over the datasheet some more. What microcontroller are you using? How often do you assert chip select? \$\endgroup\$
    – Mark
    Apr 26, 2016 at 6:44
  • \$\begingroup\$ Also, How much faster is CLK than SCLK? Does your delay after the command but before the read meet the t-sdecode timing requirement? (meaning: maybe the data isn't yet ready? Are you using the ~DRDY signal? \$\endgroup\$
    – Mark
    Apr 26, 2016 at 7:04
0
\$\begingroup\$

I've got it working. Thanks to everybody. I will edit this answer when I figure out what I did wrong so it is useful to other people.

\$\endgroup\$

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service and acknowledge you have read our privacy policy.

Not the answer you're looking for? Browse other questions tagged or ask your own question.