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I am confused about current mirror. Given this circuit

schematic

simulate this circuit – Schematic created using CircuitLab

it makes sense to connect the drain to the gate in order to make their voltage the same to bias according to the equation

$$I_{DS} = \frac{\beta}{2}(V_{GS}-V_{TH})^2$$

then

$$V_{GS} = V_1 - V_{R_1} = V_1 - R_1I_{DS}$$

So having the line connecting drain and gate is necessary to define \$V_{GS}\$ and \$I_{DS}\$

However in this this circuit, I can't understand what is the point having that line connecting drain and gate. For MOSFET, there is no current flow to gate and be so \$I_{DS} = I_1\$. By that I can already calculate \$V_{GS}\$ and \$M_2\$ have the same \$V_{GS}\$ as \$M_1\$ that make it a current source. So, what is the point of having that line here?

schematic

simulate this circuit

From what I understand, the point of current mirror is to make the \$V_{GS}\$ unchanged and apply voltage to \$M_2\$ large enough to make it in saturated region that make it behave nearly like a current source. So in this circuit, \$V_{GS}\$ is archived by the current source \$I_1\$ already, then why there must be a line connecting drain and source together?

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  • \$\begingroup\$ +1 This has bothered me for some time as well. I had come to accept that in microelectronics a "current reference source" was actually more like a current sink in a given polarization scheme, or anything more similarly modeled by the first schematic... the current source would then be a mathematical abstraction to assume this current is constant. Would like to read more thorough answers. \$\endgroup\$ – Vicente Cunha Apr 26 '16 at 20:33
  • \$\begingroup\$ Perhaps such line exists to guarantee that M1 is in the saturation region? \$\endgroup\$ – Vicente Cunha Apr 26 '16 at 20:38
  • \$\begingroup\$ Without M1's gate-to-drain connection, what is to stop the gate voltage drifting to -20 V? Or +50 V, for that matter? \$\endgroup\$ – The Photon Apr 26 '16 at 20:47
  • \$\begingroup\$ Thank, I think that makes sense to me. \$\endgroup\$ – aukxn Apr 26 '16 at 20:49
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The connection is basic to how a current mirror works. The two gates are connected together so that both FETs are driven to the same level. This assumes well-matched FETs, as would be the case with them being next to each other on the same IC.

The way the current mirror works is that the desired current is forced D-S thru M1. With its gate connected to its drain, the gate will automatically be driven to whatever it takes to support the desired current. This same voltage is then applied to the gate of M2, which in theory then allows the same current.

The purpose of M1 is to provide the right gate voltage for the desired current. The D-G connection is the feedback that allows that, in fact requires that, to happen.

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You can see that, in the first circuit, the drain-to-gate connection allows you to write an equation involving both the gate-source voltage as well as drain current through M1 (the second equation you wrote): this gives you space to choose proper values for Vgs, V1 and R1 in order to obtain the Id you want (remember that a current mirror serves the purpose of basically drawing a known current from M2's drain).

In the second circuit you can't do anything like that. You just impose Iout through the choice of I1. But an ideal current generator is just a mathematical abstraction, it means nothing in the physical world. It just represents a real object (like the one in the first picture) that sort of emulates the behavior of the ideal one.

To get to the point: the connection in the second picture is, in theory, useless, assuming I1 is ideal. In reality it is not ideal, of course; it is usually built with a circuit like the one with V1 and R1. So the connection is just a remainder of that.

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