What is the use of the line connecting drain and gate in current mirror using voltage bias?

I am confused about current mirror. Given this circuit simulate this circuit – Schematic created using CircuitLab

it makes sense to connect the drain to the gate in order to make their voltage the same to bias according to the equation

$$I_{DS} = \frac{\beta}{2}(V_{GS}-V_{TH})^2$$

then

$$V_{GS} = V_1 - V_{R_1} = V_1 - R_1I_{DS}$$

So having the line connecting drain and gate is necessary to define $V_{GS}$ and $I_{DS}$

However in this this circuit, I can't understand what is the point having that line connecting drain and gate. For MOSFET, there is no current flow to gate and be so $I_{DS} = I_1$. By that I can already calculate $V_{GS}$ and $M_2$ have the same $V_{GS}$ as $M_1$ that make it a current source. So, what is the point of having that line here? simulate this circuit

From what I understand, the point of current mirror is to make the $V_{GS}$ unchanged and apply voltage to $M_2$ large enough to make it in saturated region that make it behave nearly like a current source. So in this circuit, $V_{GS}$ is archived by the current source $I_1$ already, then why there must be a line connecting drain and source together?

• +1 This has bothered me for some time as well. I had come to accept that in microelectronics a "current reference source" was actually more like a current sink in a given polarization scheme, or anything more similarly modeled by the first schematic... the current source would then be a mathematical abstraction to assume this current is constant. Would like to read more thorough answers. – Vicente Cunha Apr 26 '16 at 20:33
• Perhaps such line exists to guarantee that M1 is in the saturation region? – Vicente Cunha Apr 26 '16 at 20:38
• Without M1's gate-to-drain connection, what is to stop the gate voltage drifting to -20 V? Or +50 V, for that matter? – The Photon Apr 26 '16 at 20:47
• Thank, I think that makes sense to me. – aukxn Apr 26 '16 at 20:49