Single event upsets are no longer a thing of space nor aircraft; we have been seeing them happen on the surface for over a decade, maybe two by now.
As mentioned though, at least in space applications we deal with upsets using triple voting (each bit is really three, and a two thirds vote wins, so if there is one that changes the other two will cover it.). And then ECC or EDAC, with scrubbers that go through the RAM at a rate higher than the predicted single event update rate to clean single event upsets (ones that actually push the two thirds vote wrong).
Then there is total dose; over time the material just gets too radioactive to work, so you use enough material to exceed the life of the vehicle. Not something we worry about on the surface normally. (And latchup) Using three/multiple sets of logic in parallel is/was a way to try to not have to use traditional rad-hard tech, and well, you can find how well that is working out.
The folks that used to know how to make stuff for space have for the most part retired or moved on, so we have a number of programs making space trash now. Or treating space like earthbound products, instead of trying to make everyone of the work and have a controlled re-entry and burnup, we now expect a certain amount of space trash out of every constellation.
We do see upsets on the surface. Any memory stick (DRAM) you buy has a FIT, Failures In Time, and any chip with RAM in it (all processors, many others), will have a FIT spec as well (for the RAM (SRAM) blocks). RAM is more dense and uses smaller transistors, so it is more susceptible to upset, internally created or external. Most of the time we don't notice or care as the memory we use for data, watching a video, etc. is written, read back and not used again before it sits long enough to have an upset. Some memory, like one holding a program or the kernel, is more risky. But we have long been used to the idea of just rebooting our computer or resetting/rebooting our phone (some phones/brands you would have to regularly remove the battery periodically). Were these upsets or bad software or a combination?
The FIT numbers for your individual product may exceed the life of that product, but take a large server farm, you factor in all the RAM or chips or whatever and the MTBF goes from years or orders past that, to days or hours, somewhere in the farm. And you have ECC to cover what you can of those. And then you distribute the processing load with failovers to cover the machines or software that fails to complete a task.
The desire for solid state storage, and the move from spinning media has created a problem related to this. The storage used for SSDs (and other non-volatile storage) to get faster and cheaper, is much more volatile than we would like and relies on EDAC, because we would be losing data without it. They throw a lot of extra bits in and ecc the whole thing, doing the math to balance speed, cost and longevity of storage. I don't see us turning back; folks want more non-volatile storage everywhere that fits in a tiny package and doesn't dominate the price of the product.
As far as normal circuits go, from the beginning days of using transistors for digital circuits to the present, we pass through the linear portion of the transistor and use it as a switch, we bang it between the rails with some excess to insure it sticks. Like the light switch on your wall, you flip it more than half way a spring helps the rest and holds it there. This is why we use digital and not try to live in the linear region; they tried early on, but failed. They couldn't stay calibrated.
So we just slam the transistor into its rails and both sides of a signal will settle by the next clock cycle. Great pains are taken, and the current tools are significantly better than they used to be, in doing the analysis of the chip design, to see that by design there is margin on the timing. Then testing each die on each wafer (that and/or after packaging), to see that each chip is good.
Chip tech relies heavily on statistics based on experiments. When you overclock your CPU, well you are pushing that margin, stay within the advertised clock rate, temperature, etc. and your chances are significantly lower of having problems. A 3 GHz xyz processor is simply a 4 GHz chip that failed at 4 GHz but passed at 3 GHz. The parts are speed graded basically from a production line.
Then there are the connections between chips or boards, and those are subject to problems as well, and lots of time and effort go into making standards and board designs, etc, to mitigate error on those interfaces. USB, keyboard, mouse, HDMI, SATA, and so on. As well as all the traces on the board. On and off the board you have crosstalk issues; again, lots of tools are available if you use them as well as experience in avoiding the problems in the first place, but yet another way where we may not see the ones and zeros be fully engaged.
None of the technologies, even space, are perfect. It only has to be good enough, enough of a percentage of the product has to cover enough of the expected life span of the product. Some percentage of the smart phones have to make it at least two years, and that's it. Older foundries or technology has more experimental data and can produce a more reliable product, but it is slower, and may not be new designs, so there you go. The cutting edge is just that, a gamble for everyone.
To your specific question, the transistors on each end of a signal are pushed quickly through their linear region and lean into one of the rails. Analysis is done on every combinational path to determine that it will settle before the clock at the end of the path latches it, so that it is truly made a zero or one. The analysis is based on experiments. The first chips of a product line are pushed beyond the design boundaries, schmoo plots are made to determine there is margin in the design. Variations on the process are made and/or individual candidates are found that represent the slow and fast chips. It is a complicated process and some have more material some have less, running faster but using more energy or running slower, etc.
You push those to the margins as well. And basically get a warm fuzzy feeling that the design is okay to go into production. JTAG/boundary scan are used to run random patterns through the chips between each latched state to see the combinational paths are all solid for a design. And where there are concerns, some directed functional tests may happen as well. Further testing of the first silicon and perhaps random testing to make sure the product is good. If/when failures occur, that may push you back to more functional tests on the production line. It is heavily dependent on statistics/percentages. 1/1000000 bad ones getting out may be okay or 1/1000 or whatever; it depends on how many you think you will produce of that chip.
The vulnerabilities are as mentioned here and with others. First the chip itself, how good was the design and the process, how close to the margin is the weakest path of a specific chip in the product you bought. If too close to the edge then temperature change or other can cause timing problems and bits will latch data that has not settled into a one or zero. Then there are single event upsets. And then there is noise. again stuff already mentioned...