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I am at the moment trying to interface with DRAM on my Xilinx Zynq device such that I am capable of moving a large amount of data from the processing system (PS) side to the programmable logic (PL). The size of the data is around 3 mb, for which it most likely is the dram i have to interface.

The examples i've found on the net seem to usually tackle this problem by either sending 32 bits multiple times back and forth, which just seems a bit inefficient.

How do I possible most effectively send a large dataset from the PS to PL?

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    \$\begingroup\$ Do you realize that it may only be you that understands what "ps", "dr", "pl" and "zynq" mean?? You are far more likely to get some answers if you were to generalize your question and spell out more clearly what these things mean. \$\endgroup\$ – Michael Karas Apr 27 '16 at 8:12
  • \$\begingroup\$ Ahh.. sorry.. Hope the edits makes it a bit more understandable.. \$\endgroup\$ – test Apr 27 '16 at 8:20
  • \$\begingroup\$ A block diagram would help. Note that interfacing to an external DRAM still involves moving bits back and forth in chunks, just that they're more likely to be 64 or 128 bit chunks. \$\endgroup\$ – pjc50 Apr 27 '16 at 8:30
  • \$\begingroup\$ ... Couldn't the data be written to some specific memory address, and such that the PL only reads the data from those address? \$\endgroup\$ – test Apr 27 '16 at 8:40
  • \$\begingroup\$ Thus utilize the full memory of the dram rather that part of it.. 32 bit.. \$\endgroup\$ – test Apr 27 '16 at 8:43
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The interconnect between the Processing System and Programmable Logic is limited by the bus width of the AXI interface.

It sound like you are looking for a way of passing a buffer directly from software to the PL all in one go, rather than individual write operations. If this is the case I would suggest looking into using the Direct Memory Access (DMA) IPs provided by Xilinx. They should allow you to segment off a subset of the PS RAM and access it directly from the PL.

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  • \$\begingroup\$ Yes.. Exactly.. but haven't found any documentations that addresses this issue... \$\endgroup\$ – test Apr 27 '16 at 21:18
  • \$\begingroup\$ Perhaps this example project for the ZYBO would be helpful. github.com/Digilent/ZYBO/tree/master/Projects/hdmi_out It uses the VDMA to pass data from linux out HDMI and VGA. \$\endgroup\$ – ks0ze Apr 28 '16 at 13:18

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