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I am trying to understand the inner workings of a CLB in an FPGA but I can't seem to find out exactly how the routing multiplexers WITHIN the CLB work. Well, I understand how they work and what they do but I can't seem to find out where the information to configure the multiplexers is stored.

enter image description here

This picture is from a Xilinx spartan-3 manual. I understand that the configuation data loads values into the LUT and sets the mux to choose routing but if I'm not mistaken the chosen signal to the mux needs to be consistently on or off, i.e. the mux has no memory. This selection information must be stored somewhere, but where?

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  • \$\begingroup\$ Are you getting confused between the user logic gates and config bit stream that programs the sram switch matrix that is making the connections between various routes? Wouldn't the registers or combinatorial logic feed the sel lines to mux? \$\endgroup\$ – shparekh Apr 29 '16 at 5:20
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Looking at a more detailed description of the slice (on page 204 of this UG) will provide us these details. As you can see, the select signal for the FiMUX comes from the BY input to the top half of the slice and the F5MUX is controlled by the BX input to the bottom half. These two inputs have additional functions and are described on page 207 of that same PDF as:

Bypass to or output (SLICEM) or storage element, or control input to F5MUX, input to carry logic, or data input to RAM (SLICEM)

and

Bypass to or output (SLICEM) or storage element, or control input to FiMUX, input to carry logic, or data input to RAM (SLICEM)

Detailed CLB schematic

Of course, this is specific to the Spartan-3, which you mention in your question. However, in general, wide function multiplexers (such as MUXF7/MUXF8 in Virtex-5/Virtex-7) are driven from an external input (such as SELF7 for more recent FPGAs that have LUT6's). This is a result of the fact that these multiplexers are used to implement wide functions. Since the function input needs to come externally (since a 7-input function with a fixed input is no better than a 6-input function that fits into the LUT6), it is logical that it cannot be driven by simply a configuration bit.

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The majority of routing looks like MUX selections based on a fixed bitstream. Below is a fuse chart for a Manhattan-style FPGA that I made that was very similar to an older Xilinx 4000 series (Choices made because I have the graph router). The CLB contains 4-BLE blocks. The truth table from the LUT has 16-bit with inputs form the MUXes on the input lines that compose the BLE.

This means that the LUT selection is dynamic but the bit configuration is static; however, you can have dynamic logic but you take a speed hit because the state bits are actually overdriven for the nFET-based MUX trees.

CLB fuse chart

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  • \$\begingroup\$ It looks like the OP is referring to wide-function multiplexers designed to extend the width of a possible function efficiently from the width of an LUT. Still, upvoted as I think this is a helpful answer discussing multiplexers in general as seen in an FPGA architecture. \$\endgroup\$ – nanofarad Apr 28 '16 at 16:47
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There is actually some memory that controls the mux, in most FPGAs it's sram, some CLBs use eeprom and some low power CPLDs use flash, it's the memory that's being programmed when the chip is configured, it's not really user accessable as each manufacturer uses their own special way of structuring the configuration files but the configuration files program those muxes, configure clocks and preload the LUTs and user memory (if present)

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  • \$\begingroup\$ Yes, but at runtime there needs to be a persistent signal to that mux to keep selection constant. Does that persistent signal come from SRAM during runtime or somewhere else? \$\endgroup\$ – Nick Apr 28 '16 at 1:51
  • \$\begingroup\$ Yep, each mux has a few bits of dedicated ram to retain its state. Every connection, every reset, every bypassable inverter, each has a little bit of ram to hold its cojfig data. All this memory adds up, Stratix V fpgas can have half a gigabit of config memory spreadout over hundreds of millions of muxes \$\endgroup\$ – Sam Apr 28 '16 at 1:56
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    \$\begingroup\$ Except in this case, the mux input in question is driven from the FPGA fabric - it's not a static mux that's only set during configuration. Other muxes will be set with configuration bits, though. \$\endgroup\$ – alex.forencich Apr 28 '16 at 2:27
  • \$\begingroup\$ Could you provide a source that specifies that the select input for F5MUX and FiMUX on Spartan-3 are driven by configuration cells and not just BX/BY? If they are in fact static then they provide no benefit since they don't work as wide function multiplexers and just serve to twist routing around in odd ways. \$\endgroup\$ – nanofarad Apr 28 '16 at 14:09

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