I am trying to understand the inner workings of a CLB in an FPGA but I can't seem to find out exactly how the routing multiplexers WITHIN the CLB work. Well, I understand how they work and what they do but I can't seem to find out where the information to configure the multiplexers is stored.
This picture is from a Xilinx spartan-3 manual. I understand that the configuation data loads values into the LUT and sets the mux to choose routing but if I'm not mistaken the chosen signal to the mux needs to be consistently on or off, i.e. the mux has no memory. This selection information must be stored somewhere, but where?