# VHDL - passing through INOUT ports

If I need to wrap an existing, previously top-level VHDL design for an FPGA with INOUT ports in another new top-level entity... what's the proper way to pass through PART of an INOUT port?

Usually, I'd just remove the INOUT from the non-top layer and replace it with directional ports... but my client wants to keep that code entirely unchanged (so the HDL supports two different board designs).

Say entity old_top_level has a port SPARE_IO : INOUT std_logic_vector(7 downto 0). Another entity new_top_level has SPARE_IO_WRAPPED : INOUT std_logic_vector(7 downto 0).

I need to redirect a single element of SPARE_IO.

Will the following work (defined in the body of new_top_level):

SPARE_IO_WRAPPED(6 downto 0) <= SPARE_IO(6 downto 0);
SPARE_IO(6 downto 0) <= SPARE_IO_WRAPPED(6 downto 0);
SPARE_IO(7) <= SOMETHING_ELSE;


It seems to compile, but that's not saying much.

EDIT I edited to clarify the INOUT signal isn't completely passed through so I can't just use the PORT MAP.

• I wonder if the most "proper" solution might be to give the module a non- top-level structure (ie, separate ports) and provide a trivial wrapper for the stand-alone usage case. – Chris Stratton Dec 2 '11 at 18:43
• @ChrisStratton It looks to me like that would be the solution. Was this question ever fully resolved? – trayres Jan 1 '13 at 19:40

Inouts can exist internally or externally. Indeed in reality they don't exist as physical gates, in both cases they are two gates in oposite directions in parallel.

Internally inout is usually imlememnted as an array of OR gates for the driver and multipel connections to AND gates for the receivers. There is no tristate internally.

Externally inout is usually two gates, the output one being able to be tristated by some common select signal.

VHDL does not care about 'internal' or 'external' signals.

So long as the VHDL syntax inferrs some means of deciding which device is being selected for access to the inout, the same code can be used as a top level or lower level module.
bus<=myoutdata when RD='1' else (others=>'Z');