If I need to wrap an existing, previously top-level VHDL design for an FPGA with INOUT ports in another new top-level entity... what's the proper way to pass through PART of an INOUT port?
Usually, I'd just remove the INOUT from the non-top layer and replace it with directional ports... but my client wants to keep that code entirely unchanged (so the HDL supports two different board designs).
old_top_level has a port
SPARE_IO : INOUT std_logic_vector(7 downto 0). Another entity
SPARE_IO_WRAPPED : INOUT std_logic_vector(7 downto 0).
I need to redirect a single element of SPARE_IO.
Will the following work (defined in the body of new_top_level):
SPARE_IO_WRAPPED(6 downto 0) <= SPARE_IO(6 downto 0); SPARE_IO(6 downto 0) <= SPARE_IO_WRAPPED(6 downto 0); SPARE_IO(7) <= SOMETHING_ELSE;
It seems to compile, but that's not saying much.
EDIT I edited to clarify the INOUT signal isn't completely passed through so I can't just use the PORT MAP.