I am designing a DC/DC converter. I chose the fullbridge topology. The requirements are as follows:
- Vin = 75 - 125 Vdc
- Vout = 200V
- P = 600W
- Fs = 100 Khz
I use ZVS for soft switching. The problem is the big spike in the Vds on the MOSFETs.
- signal A is the up - left mosfet
- signal B is up - right mosfet
- signal C is down - left mosfet
- the signal D is down - right mosfet
I see that the voltage spike is generated in right leg transition (when D switch is falling). The same spike occurs on the primary current. Why does it occur? Is the problem in the primary or secondary?
I provide a large time for discharging the parasitic capacitances (over 400ns). Which components oscillate in my design?