I am using 2 interrupts on LPC1778. One for CAN and one for timer. The CAN interrupts whenever a new message is received. The timer interrupts every 200uS. The priority for timer interrupt is the highest(i.e NVIC Priority=0). My doubt is, if a CAN message arrives, and im in the ISR, suppose a timer interrupt occurs while in CAN ISR, will the timer interrupt ISR be executed and then return back to CAN ISR? Or,will CAN interrupt be completed before timer interrupt is executed. Does priority apply only if both interrupts occur at same time or does priority apply for setting which interrupts cant be masked under any circumstance. Because,its very critical that timer interrupt has to execute every 200uS under any circumstance.
Refer to the fine User Manual. The LPC1778 microcontroller contains an ARM Cortex-M3 core which includes the nested vectored interrupt controller (NVIC) peripheral. The key word here is "nested", which means that the interrupt controller supports nested exceptions and interrupts, which means that an active interrupt can be preempted by a higher priority interrupt. Search the User Manual for the terms "nest" and "preempt" to learn more.
You'll have to configure the interrupt controller and prioritize the interrupts appropriately for preemption to occur. Perhaps you'll choose to use the SysTick exception for your timer so that it is higher priority than the CAN interrupt. Or if you use an interrupt for the timer as well then you'll need to configure the group priority (see section 22.214.171.124) of the interrupts to ensure the timer ISR can preempt the CAN ISR.