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I am using 2 interrupts on LPC1778. One for CAN and one for timer. The CAN interrupts whenever a new message is received. The timer interrupts every 200uS. The priority for timer interrupt is the highest(i.e NVIC Priority=0). My doubt is, if a CAN message arrives, and im in the ISR, suppose a timer interrupt occurs while in CAN ISR, will the timer interrupt ISR be executed and then return back to CAN ISR? Or,will CAN interrupt be completed before timer interrupt is executed. Does priority apply only if both interrupts occur at same time or does priority apply for setting which interrupts cant be masked under any circumstance. Because,its very critical that timer interrupt has to execute every 200uS under any circumstance.

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  • \$\begingroup\$ The microcontroller can priorize them. No problem on this side. Now, what is not trivial, is to make sure your OS (if you develop yours), is reentrant and can handle this. If you reuse an existing OS, tell us what it is. \$\endgroup\$ – dim lost faith in SE Apr 29 '16 at 11:06
  • \$\begingroup\$ Im not using any OS. Just the LPC1778 as is. \$\endgroup\$ – AlphaGoku Apr 29 '16 at 11:14
  • \$\begingroup\$ Ok, then you have to take great care of the way you write both ISR functions, to not affect the CAN ISR working registers/variables in case it is interrupted. Now for the configuration of the NVIC, it should be just masking, but I'm not an expert. Relevant answers should come soon. \$\endgroup\$ – dim lost faith in SE Apr 29 '16 at 11:25
  • \$\begingroup\$ Im using timer interrupt to generate critical pulses. Thats y timer ISR cant be halted while another ISR is executing. \$\endgroup\$ – AlphaGoku Apr 29 '16 at 11:29
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Refer to the fine User Manual. The LPC1778 microcontroller contains an ARM Cortex-M3 core which includes the nested vectored interrupt controller (NVIC) peripheral. The key word here is "nested", which means that the interrupt controller supports nested exceptions and interrupts, which means that an active interrupt can be preempted by a higher priority interrupt. Search the User Manual for the terms "nest" and "preempt" to learn more.

You'll have to configure the interrupt controller and prioritize the interrupts appropriately for preemption to occur. Perhaps you'll choose to use the SysTick exception for your timer so that it is higher priority than the CAN interrupt. Or if you use an interrupt for the timer as well then you'll need to configure the group priority (see section 39.3.3.6) of the interrupts to ensure the timer ISR can preempt the CAN ISR.

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  • \$\begingroup\$ Im using the CMSIS driver . For CAN-> NVIC_SetPriority(CAN_IRQn,1);NVIC_EnableIRQ(CAN_IRQn); For Timer->NVIC_EnableIRQ(TIMER0_IRQn);NVIC_SetPriority(TIMER0_IRQn,0); This is all that required right,to ensure timer is never halted? \$\endgroup\$ – AlphaGoku Apr 29 '16 at 13:19
  • \$\begingroup\$ A higher priority will preempt the lower priority,and after the higher priority is done,it will return to the lower priority right? \$\endgroup\$ – AlphaGoku Apr 29 '16 at 13:35
  • \$\begingroup\$ Yes, the lower priority ISR will resume after the higher priority interrupt is complete. I don't know whether those function calls are enough setup. I'm skeptical because they don't appear to include setup of the priority groups and I'm unsure whether 0 and 1 are valid priority values. You'll have to read the manual, and then test your code. It would be helpful to review some examples from the vendor, NXP. \$\endgroup\$ – kkrambo Apr 29 '16 at 18:21
  • \$\begingroup\$ Priority groups is only for same priority interrupts right. I have explicitly made timer as a higher priority \$\endgroup\$ – AlphaGoku Apr 30 '16 at 7:23
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    \$\begingroup\$ Read section 39.3.3.6. It seems very clear. "Only the group priority determines preemption of interrupt exceptions. When the processor is executing an interrupt exception handler, another interrupt with the same group priority as the interrupt being handled does not preempt the handler." \$\endgroup\$ – kkrambo May 1 '16 at 15:27

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