NPN vs PNP current limiter

So I'm trying to design two mirroring current limiters for a +-15 volt power supplies.

I don't understand why these two circuits don't behave more like each other.

The PNP circuit has +15 on the top and ground on the bottom and

The NPN has ground on top and -15 at the bottom.

The npn limits at around 600mA which is what we expect ,but I'm not sure why the PNP is 450mA.

I don't understand why the Vbe on the PNP is only 0.46 V and not around 0.65.

• Just asking the obvious, but you Load2 is 0.001 times Load1. Is that deliberate? Commented Apr 29, 2016 at 14:54
• As long as the load is such that it would require more current at 15V than the limiter it makes no difference. Commented Apr 29, 2016 at 15:02
• Why don't you tabulate side by side the differences - it's really hard to make comparisons otherwise. Commented Apr 29, 2016 at 16:25
• The funny thing is that when I built a quick breadboard prototype the currents are the same so maybe the software model of the pnp is wrong. Commented Apr 29, 2016 at 17:06
• Another perhaps obvious question, but if you are making a two-terminal current limiter, why wouldn't you just flip it over to get the opposite polarity rather than trying to use complementary transistors? Commented Apr 29, 2016 at 20:17

Looking at the datasheet, we can get the current gain for both PNP and NPN:

It seems that the NPN variant gives sightly higher current gain than the PNP variant. There are more parameters that differ, probably the VBE, etc. which is a reason why both configurations won't give same results.

1Ω Resistor Sense2 is passing 455mA so must be dropping 0.455V, and Q6 VBE must also be 0.455V. This is much lower than expected (should be ~0.65V) so I suspect the D45H11G model is wrong.

To confirm, I measured the Base-Emitter voltage of several D45H11 transistors drawing ~60mA with 0.9V from Collector to Emitter. All 3 samples had a VBE of 0.655V.

This current limiter is very similar to a SCR structure so generally to avoid oscillations with the load it is employed with an emitter resistor on both transistors so the gain will be lower. Probably the simulator computes the base current that flows thru the opposite transistor so an unpredictable working point is computed. Try with a 10 to 100 R in series with emitter of the Q4 or Q6 and probably the results will be more similar.

I simulated your PNP circuit with LTSpice, using the standard model from LTSpice for the D45H11. I got similar results to you, with a current of 452mA through the load.

On Semi have a number of different spice models for the D45H11. I used this one for the MJD45H11. You can either change your transistors to MJD45H11's or change the model statement to D45H11. In LTSpice I simply pasted the .model statement onto the schematic.

Using the MJD45H11 model I get a current of 712mA through the load.

The conclusion has to be that the standard model for the D45H11 is wrong.