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What is meant by "Bulk condition" in a semiconductor?

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It simply refers to the part of the wafer/die that has not received additional implants or processing. Except when ... see below.

In the case of a transistor, it the well implant that is being referred to. Again in this case it is the structure that the source/drain implants go into and is the background condition.

What might be confusing is that there is a "bulk" for the wafer and a "bulk" for the transistor with the transistor "bulk" actually being an implant into the wafer bulk through the well implants.

The common thread is that a "bulk" is therefore a background level of doping in a structure that is not that electrically active (i.e. you tend to have DC values applied - but not always).

It is considered to be more of a turn of phrase than a strict technical delimiter.

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  • \$\begingroup\$ Okay, could it also be see as the bulk part of the semiconductor is acting like a resistor? Impliying it would be increasing with voltage across contacts? \$\endgroup\$
    – Arsenal123
    Apr 29 '16 at 15:03
  • \$\begingroup\$ "Bulk" is also distinguished from the surfaces (where two semiconductors meet, or where the semiconductor meets an oxide or air). At the surfaces there may be additional localized states that change the carrier behavior. \$\endgroup\$
    – The Photon
    Apr 29 '16 at 15:45
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The "bulk" is the well connection, but it's very colloquial. On a depleted SOI process, we don't have a "bulk" connection per se; however, if you have a non-SOI process, you will hear "bulk" referred to often in regards to the wafer ties, specifically when you are dealing with nfets because they are in the p-doped substrate. When you look at an analog MOSFET, you will have designers throw around the "bulk" for the relative reference for the wafer substrate voltage, and then your WELL ties (if you have WELLs) are from where you reference your threshold voltage.

In the nFET cross section below, the Vb is the bulk connection that is a P+ implant into a p-substrate of the wafer. nFET

From the TOP, this will look something like this: enter image description here

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