Yes this question is related to MCP4131 which is a 8 pin digital potentiometer. I have never seen/heard/used multiplexed SPI before so am trying to clear some confusions. The datasheet shows connection as shown below:

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Now lets look at the timing diagrams which is where the confusion lies. They are found starting from page 44:

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The first and third waveforms show SDI and SDO being driven at the same time. Certainly the MCP4131 cannot output and input signal at the same time since in SPI a signal is latched at a specific edge of SCK. In this case it is the rising edge. So do I understand correctly that for MCP4131 only the second waveform is applicable since the first and third do not make sense with multiplexed SPI?

With multiplexed SPI and a high voltage mode on CS this looks like a mysterious device. Why make life harder by squeezing so much functionality in such a small package?

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    \$\begingroup\$ I would imagine it's much like normal 3 wire spi, half duplex communications, data can only go one way at a time. \$\endgroup\$ – Sam Apr 29 '16 at 23:47
  • \$\begingroup\$ Yes, it is forcing a full-duplex protocol into a half-duplex application. The difficult part is that a normal SPI device cannot receive data without transmitting data. Hence the resistor. \$\endgroup\$ – Mark Apr 30 '16 at 1:32

The Microchip device is made with separate MISO and MOSI pins (aka (probably) SDO and (probably) SDI respectively) as well as multiplexed MISO and MOSI pins. It is always better to call these nets by MISO and MOSI as these names do not need to be reversed at the far end of the SPI bus. A practice that leads to endless confusion.

As for what the figures mean:

Figure 6-3 is for a Microchip device with separate MISO and MOSI pins. Figure 6-5 is for a Microchip device with multiplexed MISO and MOSI pins. Figure 6-7 is a feature where the master SPI device supplies an abbreviated (command which is only 8 bits long) SPI message to the slave SPI device (for turning up or down the potentiometer). However as there is activity on what is labeled as the "SDO" line it would appear to apply to the Microchip device with separate MISO and MOSI pins.

As for how multiplexed SPI works:

The MCP41X1 is expected to back drive the MISO net when it needs to send data in the 2nd half of a SPI transaction. That is, the MCP41X1 is expected to eclipse any MOSI net activity because the MOSI and MISO net are separated by R1.

As for choosing or not choosing multiplexing MISO & MOSI style chips:

The MCP41X1 8 pin package allows access to both sides of the potentiometer as well as the wiper. It offers this at the expense of multiplexing the MISO & MOSI pins.

The MCP41X2 8 pin package allows for separate MISO & MOSI pins. It offers this by only offering one side of the potentiometer and the wiper.

(MOSI = Master Out Slave In) (MISO = Master In Slave Out)

  • \$\begingroup\$ So that means that for a given cycle of SCK, the slave shall either be input and thus MISO shall read the MOSI i.e loop back from microcontroller. However for the cycle where the smart pull up in the slave is activated, the MISO shall be driven by the slave only and voltage from MOSI shall not be forced on it due to the resistor. Therefore, the slave shall not output as well as input data in the same clock cycle. \$\endgroup\$ – quantum231 Apr 30 '16 at 9:16
  • \$\begingroup\$ That is my understanding. That a MISO / MOSI multiplexed SPI device does not drive and sense at the same time. \$\endgroup\$ – st2000 Apr 30 '16 at 13:04
  • \$\begingroup\$ OK, I guess I will put together the setup and carry out the mad scientist experiment with this device. thanks. \$\endgroup\$ – quantum231 Apr 30 '16 at 20:27

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