# How do SRAM bit line “gates” work?

I'm currently learning about the operation of 6 transistor static random access memory cells and I've hit a wall in understanding exactly how the read/write operations work. More specifically I don't get the gate transistors that control whether the cell is connect to the bit lines or not. Firstly, since the "information gates" are just single FETs, there is the problem of there being no voltage drop across them, so ultimately they don't act as gates at all. A simple solution would be to somehow connect the bit lines to ground (which seems like a terribly inefficient way to fix this problem since that would create a constant current). How do people solve this? How do you read and write data onto SRAM cells efficiently and reliably?

For a visual aid I've created an SRAM cell in a simulator to show the problem. The bit lines are the wires on the very right and left. As you can see, one of the wires has voltage while the other does not. Ideally they would both have no voltage until I activated the word line (the wire on top) which would open up the transistor "gates". Essentially the gate transistors are useless as for the moment. How do I get them to work?

SRAM cell in circuit simulator:

## migrated from stackoverflow.comMay 1 '16 at 23:32

This question came from our site for professional and enthusiast programmers.

The problem is that you have simplified your system too much, and now you're confusing yourself. There are two major problems, and a third that may be an issue.

First, it is only useful to think of SRAM as a completely digital system when the data is being stored. When you write or read the bit cell, you have an analog circuit.

Second, you only have a bit-cell, completely disconnected. You will get a different result with good models and a complete system. The bit-lines in your diagram (with the word-line low) are high-impedance nodes, meaning that something just needs to sneeze in its direction to change the voltage. However, there is nothing in your diagram that actually will change the bit-line voltage (so it stays the same).

Third, the Falstad simulator is a fun toy, but you aren't going to do IC design using it. The MOSFET model is too simplistic, and the solver method isn't accurate either. You won't be able to set a ratio of sizes between the transistors either.

Also, don't confuse "there's zero voltage across this transistor drain and source" with "this transistor is conducting". Your access transistors are probably working just fine.

As for 6T general design, you end up designing a circuit that doesn't change values during a read, but can still be written to. This is achieved by varying the drive strength of the six transistors and simulating it over various conditions to make sure the design is robust.

• I wonder if the simulator is assuming the MOSFETs have body diodes so the access transistors only block voltage from drain to source, not from source to drain. See electronics.stackexchange.com/questions/72582/… – augurar May 2 '16 at 19:00
• @augurar Falstad does not model the body diode of a MOSFET. My guess is that the model uses an "off" resistance of 100 MΩ. This is a really common simulator approach to making the circuit "solvable". You can find this as a setting in most simulators labeled as "gmin". – W5VO May 2 '16 at 21:56

Here is how your diagram should look:

Source: Wikipedia

Due to the nature of the memory cell in the middle, one of the input/output wires Q or ~Q will always have voltage. However these wires will be disconnected from the bit lines BL and ~BL unless the word line WL has voltage, due to the n-MOSFETs M5 and M6.