TVS Diode Layout

Question

I have two DB37 connectors on my board which ultimately connect to a CPLD. All of these connections/signals are inputs to the device.

To protect from ESD I am using TVS Diodes ESD9C3.3ST5G. I have the board like so:

DB37 -> Diodes -> Pullup resistor -> CPLD.

The 1K pullups are for a different purpose and are not related to ESD protection. My PCB is 4-layers with the following stackup:

1. Signals
2. Ground
3. 3.3V
4. Signals

The diodes connect to the ground using a via. The trace to the via is thick - thicker than the trace to the CPLD. The ground plane is completely unbroken with the exception of through-hole pads and vias. I assume this protects against at least some mild ESD. But what do I need to do further? This is not a commercial device and will be used internally - however I do need it to be reliable.

1. One of the things I thought was to add series resistance (22 Ohms or so) between the diode and the CPLD. However, as all the pins on the CPLD are inputs so they're already high-impedance. The ESD should go towards the ground via the TVS diode. Is my assumption correct?
2. I have also read that adding a capacitor in parallel with the diode can help. My signals aren't high speed so this shouldn't distort them much. However, do note that I'll have to 74 of these caps as I have 74 signals. So before I went and added these I wanted to know if this was worth it.

Here's a closeup of the layout:

Finally, one last question - the above described the input side of my board. The output is similar in the sense that I have two further DB37 connectors and a CPLD. In this case, the CPLD's pins are outputs.

The layout is like so: CPLD -> MOSFET -> DB37

In this case, I don't have any diodes. However, as I've read recently, MOSFETs are far more sensitive to ESD than other devices, should I add diodes here as well? The MOSFET's drain is connected to the DB37. This DB37 is then connected to the input-side DB37 described earlier.

If a MOSFET is on, it's drain-to-source resistance would be quite low. And as such, this could prove an attractive path for the ESD pike to go through rather than the TVS diodes on the other end. Am I correct that I should add TVS diodes here as well? If so, oh boy, 72 more diodes!

Answer 1

The TVSs on the inputs makes sense and your layout looks reasonable. The question is how far do you want to go to get what level of protection? It's a probability game. Just the TVSs should take care of most ESD events.

If you want to go a little farther, put a resistor in series with each input before the TVS, not between the TVS and the CPLD. This gives the TVS some minimum guaranteed impedance to work against. Going even farther, add a little capacitance accross the TVS. That will slow down the edges of really fast spikes so that the TVS can catch them effectively. It goes on and on, with each level of higher complexity decreasing the probability a damaging event will be encountered even further.

Only you know what environment these boards will be in, the cost of the extra board space, and the cost of failure.

Answer 2

The layout in the O.P. makes sense.

One of the things I thought was to add series resistance (22 Ohms or so) between the diode and the CPLD. However, as all the pins on the CPLD are inputs so they're already high-impedance. The ESD should go towards the ground via the TVS diode. Is my assumption correct?

Your assumption holds for this layout. It's a correct layout, because there's no stub between the trace and the TVS pad. An ESD pulse has a very fast raise time and plenty of current. The parasitic inductance in the stubs can present enough impedance and create large voltage gradients. Don't assume that traces are ideal conductors when it comes to ESD pulse.

[source: ESD protection layout guide (TI app note slva680) ]

L1 should be as small as practical. L4 should be much larger than L1. That means that the TVS should be placed close to the exposed pin. Wide trace has a lower inductance than a narrow one. A wider trace between the connector and the TVS, and a narrow trace between the TVS and the IC makes sense.

I have also read that adding a capacitor in parallel with the diode can help. My signals aren't high speed so this shouldn't distort them much.

Yes, a capacitor can help by absorbing an ESD pulse. There are ESD-rated ceramic capacitors. Larger capacitors (larger capacitance) withstand ESD better than small ones.
Further reading: here and here.

Finally, one last question [...] should I add diodes [to the open drain outputs] here as well?

TVS protection of the MOSFET outputs is a right idea. MOSFET outputs are sensitive to ESD.
Further reading here.