# Max number of logic units / gates per logic-unit-output wire: FPGA

I couldn't find any info about this. Is there a general rule or does it change for all vendors(altera or xilinx)?

Lets assume I have a flip flop and I want to wire 10 flip-flops to its output. Normally, in my university lab using cheap (1$-2$) ICs, 10 was max value. Maybe same for FPGA? Or can it carry heavy loads like 2000 flip-flops wired to same output? Is this related to "drive strength" mentioned in verilog/vhdl? They dont mention a constraint.

In future, when I have an FPGA, I will try some floating-point compute accelerator that need to broadcast a variable to all cores.

As "Dave Tweed" commented, it must be "fanout" and he says its an implicit control by design tool. Any more info? How many gates are dedicated if it is implicitly driven?

I'm addressing inner (dynamic) parts of fpga which I will build some cores. Not the outer parts.

• The general term for what you're asking about is "fanout". In general, the FPGA design tools will handle this for you by replicating logic where necessary, so it isn't something you need to deal with explicitly. – Dave Tweed May 3 '16 at 12:19
• Are you addressing internal or external load to the FPGA? If it's external, the rules are the same as for every IC. Each pin has a maximum current which it can drive or consume. The signal's rise and fall time depend on the maximum current and the sum of all load capacities connected to the pin. For an internal load, the rules are different. The FPGA has internal buffers to drive the short- and long-lines. If needed, the synthesis algorithms will duplicate logic, flip-flops or buffers to split the load. – Paebbels May 3 '16 at 12:27
• In case you are curious, I have one design where one clock node has a fanout of 20000+ nodes. The largest non-global fanout in that design (i.e. standard routing) is about 2700. So you can connect many many things together. – Tom Carpenter May 3 '16 at 12:58
• @Tom Carpenter, does it add any latency for it? I mean, is it some tree structure under implicit things? – huseyin tugrul buyukisik May 3 '16 at 13:01
• It works out the connections itself. In my case the design runs at 250MHz and it meets the timing requirements to do so. Timing is one of the key aspects of this and the fitting tools are good enough to optimise things (location, duplication, etc.) to do its best to meet the design requirements. – Tom Carpenter May 3 '16 at 13:11