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I am novice to high speed design.

Before getting in to DDR, I recently learned about impedance matching and how it is done, likewise I learned about length matching and how it is done.(Baby steps towards Signal Integrity)

Now, I need to Place and Route a DDR system within 50x40mm. I have been asked do to it in six layers.

What are the things I will have to learn before doing this? The document I am currently using for reference is AN2582 from FreeScale Semi. Frankly speaking, I dont understand many terms and technologies mentioned in it.

So please list out the points crisply, books and links would be helpful.

Specifically I am looking for suggestions on:

1.StackUp(Gnd, Power Plane location) with reference to Impedance matching(if necessary)

2.Routing principles I will have to follow:

2a) what are the signals that needs to be Length matched in my circuit(details given below). There are 3 to 4 signals falling under the category of address and data group(adding more to my confusion).

2b) routing considerations on address, control lines.

3.Checklist after completion of the entire design.

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The third screen shot illustrates signals from Processor.(Kindly zoom-in for part numbers and bear with me)

The crystal used as clock source for Processor is 13Mhz(low speed board isnt it?)

At this time, I have no idea about rise time .

Thanks in advance.

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  • \$\begingroup\$ Clock source doesn't mean much - what's the frequency on which processor works and what is the clock frequency for DDR - if it's 13MHz you can probably route it whichever way you like it, but I doubt it is that slow. I have a Freescale MPU which is using 25MHz crystal but runs at 400+ MHz with DDR frequency that can go from under 100MHz to 133 (or so). These parameters are important because you can get away with lots on lower frequency (rules are still relatively tight, mind you), higher the frequency ... well things get pretty though fast. \$\endgroup\$ – Mihailo Dec 5 '11 at 11:52
  • \$\begingroup\$ I see a lot of discrete resistors with the same value. I hope you plan on using a resistor pack for those. It'll save space, money, and your assemblers will thank you. \$\endgroup\$ – Joel B Jan 18 '12 at 20:20
  • \$\begingroup\$ @Joel B That is actually a really bad idea for this application. You can get away with it depending on the speeds involved but its not really a good plan to mash a bunch of high speed signals through a resistor pack. It creates a lot of crosstalk, especially when using the pack for source termination. \$\endgroup\$ – Mark Jan 18 '12 at 23:41
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    \$\begingroup\$ @Mark In both the application note in your answer and in this other application note (on page 8) from the same manufacturer they seam to not recommend against using them, only that the command/address and data/data strobe signals use separate resistor packs. They even use them on their validation board. \$\endgroup\$ – Joel B Jan 19 '12 at 14:45
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I highly recommend the first thing you do is purchase High Speed Digital Design: A Handbook of Black Magic. Read it twice, then read it again :)

One important point. The crystal frequency doesn't matter here, you need to know the speed of the signals on the lines in question (which can be many times the crystal frequency). More over its actually rise / fall times that drive almost all signal integrity issues, not the digital frequency of the signal.

Designing for DDR isn't really that simple. High speed design can be a bit of a 'voodoo' art, even if you have $10,000+ simulation software. In other words, don't expect to nail the design the first time without putting in the work to understand the issues involved, a check list really won't cut it.

What I mean is, you really should start by reading the book I linked. It will give you enough background that the information in AN2582 will make sense (side note you linked the wrong pdf in the op). It will also allow you to understand the design trade offs you'll likely have to make when laying out the PCB.

That being said, here are my thoughts:

Routing Guidelines:

High level things to consider / avoid:

1) Route on a single layer, with a solid ground plane under it. Avoid vias like the plague. If this isn't possible, the DQ and ADDR groups are most critical, route those first, try to only move signals as groups to different layers.

2) Make sure you impedance match the traces: 50-60ohms, whatever comes out to the 'nicest' trace width for the design. Note the difference between differential and single ended lines and match the impedance appropriately.

3) Maintain proper signal spacing (i think 3*signal line width is preferred). This will help limit crosstalk between signals.

4) Match trace length of all related signals / groups (differential pairs, data bus, address bus, etc). Try to keep all traces to roughly the same length, that is you don't want the address group to be 1cm longer than the data group if you can avoid it.

5) Use source termination. You probably don't need parallel termination nor a Vtt given your board size and use of a single ram ic.

6) Pay special attention to Vref, it needs to be stable: well decoupled, fat traces. For a single ram module you can generate it with a simple resistor divider.

7) Don't use resistor banks for the termination, use individual resistors.

8) Expect that you'll need to 'play' with the source termination resistor values on the first prototype. Basically put a scope on the signal and try various values in the region of (trace_impedance - driver output impedance) = R. Look for the value that results in the cleanest signal (read up on eye patterns).

Signal Groups:

They are (NOTE: Taken from AN2910 and this is for a 64bit + 8bit ECC module, you don't have all these pins):

Data Group: \$MDQS(8:0), \overline{MDQS}(8:0), MDM(8:0), MDQ(63:0), MECC(7:0)\$

Address/CMD Group: \$MBA(2:0), MA(15:0), \overline{MRAS}, \overline{MCAS}, \overline{MWE}\$

Control Group: \$\overline{MCS}(3:0), MCKE(3:0), MODT(3:0)\$

Clock Group: \$MCK(5:0)\$ and \$\overline{MCK}(5:0)\$

Stack Up:

There are lots of ways to do this. Micron gives their recommendation for 6 layer stack ups with 3 or 4 signal layers in app note TN-46-14.

Really stack up is an entire topic of its own, but if your device has the 'standard' assortment of devices on it, these recommendations should work fine.

Other Stuff:

I think the rest of your questions are answered in the linked pdfs or AN2582. There is another checklist available in AN2910.

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  • \$\begingroup\$ Somewhat a side point but have you read his second book, the advanced black magic? \$\endgroup\$ – Kortuk Jan 19 '12 at 4:42
  • \$\begingroup\$ @Kortuk I haven't, I didn't know there are a new version. I don't work as much doing this type of work anymore but I'll probably pick it up anyway as I enjoyed the first book. \$\endgroup\$ – Mark Jan 19 '12 at 21:09
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I've failed the DDR design using FPGA + DDR, but still don't know which part fails. Why did You leave address lines without resistors if all the other pins have it? What wire length will be between cpu and ram? If it's longer than 2 inches (5cm), then parallel termination is needed. Clock differential pair needs 100ohm termination in all cases. Also is it low power DDR? Because common DDR chips are powered 2.5V and they have to have VRef pin, which has to be half the power supply voltage (1.25V). I'd offer You to go to www.micron.com, select any DDR memory chip and go to documents tab, there will be many documents regarding memory layout and other issues.

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  • \$\begingroup\$ as the board size is 5cm, cpu to ram length is within that limit. thanks again. \$\endgroup\$ – V V Rao Dec 5 '11 at 7:04
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The checklist from AN2826 seemed pretty understandable:

  • Minimize overall trace lengths between the MPU and DDR SDRAM. Trace lengths should be kept < 6 inches (15cm) if possible. The components could and should be placed as close as possible to the MPU, particularly the DDR SDRAM components.
  • Each DQS, DM, and DQ group of signal traces must have identical loading and similar routing to maintain timing and signal integrity.
  • Control and clock signals are routed point-to-point.
  • Trace length for clock, address, and command signals should match to within +/- 1.25cm (500mil).
  • Route DDR signals on layers adjacent to a ground plane, to minimize noise.
  • Use a VREF plane under the SDRAM. VREF is decoupled from both SDVDD and VSS (GND).
  • To avoid crosstalk, keep address and command signals separate (i.e. a different routing layer) from the data and data strobes.
  • Use different resistor packs for command/address and data/data strobes.
  • Use single series, single parallel termination (25 ohm series and 50 ohm parallel values are recommended, but standard resistor packs with similar values can be substituted).
  • Series termination should be between the MCF547x and memory, but closest to the processor.
  • Parallel termination is at the end of the signal line (close to the DDR SDRAM).
  • 0.1 uF, 1nF & 100pF decoupling capacitors (COG or NPO dielectric) are used with the termination resistor packs.
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