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I'm learning about synchronous DRAM and it often mentioned a memory controller. What exactly is the point of this? Couldn't the cpu just take the job of requesting and receiving data with its own clock? And something else that has confused me is RAM latency. How exactly does a computer wait a certain number of clock cycles to receive information? What does the computer do during these in between clock cycles?

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    \$\begingroup\$ "Couldn't the cpu just take the job of requesting and receiving data with its own clock?" Sure, but I'd rather have it doing something, you know... useful. \$\endgroup\$ – Ignacio Vazquez-Abrams May 4 '16 at 5:33
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    \$\begingroup\$ Note that usually the memory controller is a subsystem on the same physical chip as the CPU. \$\endgroup\$ – pjc50 May 4 '16 at 8:47
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    \$\begingroup\$ Early microprocessors did have to do this (see wiki) but this was cumbersome. The Z80 added special registers/circuitry to help (this bit of above link). \$\endgroup\$ – TripeHound May 4 '16 at 12:29
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A dedicated memory controller is mandatory for several reasons (built into the CPU or not). Because it is dynamic memory each memory cell has to be 'refreshed' with a strobe every 16mS or so.

With some Dram chips having gigabytes of storage, the CPU would spend all of its time refreshing the Dram. Using timed latency or handshake signals (still a known latency - or delay time to refresh the DRAM) the DRAM controller lets the CPU know when it can read or write to the DRAM.

The memory controller also handles another complicated chore, and that is allowing other devices such as a LCD driver chip to have access to the DRAM if the CPU is not demanding access. This priority tree built into the DRAM controller allows several devices besides the CPU to 'have their turn' to access the DRAM.

Synchronous simply means the CPU and DRAM controller share the same clock, or the CPU supplies the clock for read/write request.Synchronous can allow data to be moved in short burst, improving data transfer speed.

Dram memory cells use just one transistor and one capacitor to 'hold' the state (1 or 0), so a fast refresh pulse to each cell is mandatory, or the cells will forget their state and cause a CPU crash.

About 30 years ago when DRAMs first came to market crashes and data loss were common.

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You sort of answer your own question.

How exactly does a computer wait a certain number of clock cycles to receive information?

It doesn't know. It must have a memory controller that knows about the available memory. The CPU typically¹ just tries to access an external memory address, and waits for the memory controller to signal that the access is completed.

The more complex the memory gets, the more complex the controller must be, and the more complex the protocol gets. You have just started reading about synchronous DRAM, which is one step up from normal DRAM, which is one step up from the SRAM and ROM which was common before DRAM.

A memory controller was not necessary with SRAM: memory used to be faster than the CPU back in the days, so the CPU could just put an address on the bus and read/write the data directly.

Then came DRAM, which required a very simple memory controller that could multiplex the upper and lower address bus, and wait for the DRAM to finish.

SDRAM adds even more, because you can now access different pages without penalty, and after that comes DDR, DDR2 etc.

Now, a lot of this can also move in on the CPU, so you don't necessarily need a separate controller.

¹ Modern CPUs are of course extremely complex, and have several layers of caching and things going on - it's not as simple as just accessing an external address.

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