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My question is not on 'how can' but 'if can'. So I believe people with sufficient experience on any FPGA family might be able to help me out here.

Problem Statement: I need to model a very basic control system on an FPGA such that the 'plant' runs as a Verilog(HDL) module on the FPGA (not just simulation) and the controller is implemented as a C executable running on NIOS2 softcore processor on the FPGA (Altera Cyclone IVGX).

All the manuals and posts that I read which use the CAD tool (Qsys,Quartus,SOPC builder etc) take only examples of how a NIOS 2 softcore processor can be flashed on an FPGA and get it doing various stuff. But can I also have a system where the NIOS2 is being synthesized along with other Verilog(HDL) modules and interacting with any code running on the softcore processor?

I understand that by posing such a question I may provoke some for a RTFMish response, but i did scroll through the design handbooks looking for such topic but couldn't find one.

All I need to know is if this can be done so that I spend more time reading the manuals even closely than before.

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Yes, you can definitely do that. After all, the whole point of having a soft-core CPU is so that you can integrate it with custom logic.

At its heart, the NIOS processor is just another HDL module. You can instantiate it within a top-level design just like any other module.

However, I have found that the vendor tools (from both Altera and Xilinx) have developed strict formalisms for building systems that require you to wrap your custom logic in a particular interface so that their "system generator" can generate the top-level module of the chip for you and make all of the connections. It can take some time to figure out where the details of that formal interface are documented and how to use it.

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  • \$\begingroup\$ Call it my greed :). But could you help me with some resources that will help me understand the resolution mechanism as you brought out, in a more concise fashion than reading the Altera's both reference books from cover to cover. Thanks \$\endgroup\$ – sherinkapotein May 4 '16 at 12:24

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