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I'm going to use one of the PIC32MX795F512L SPI peripherals (master), 1 to 4MHz, to communicate with multiple devices (slaves):

  • Wi-Fi module MRF24WG0MA (3.3V);
  • uSD card (3.3V);
  • 9 modules with sensors and ADCs with SPI, on their own boards, connected to the main board through 10cm cables (powered by 5.0V from main board);
  • 3 external optional modules with sensors and ADCs with SPI, on their own boards, connected to the main board through 25cm cables (powered by 5.0V from main board).

I can only use one SPI in the MCU since all other have their pins already in use. I have enough pins for the CS lines.

The sensor boards can have any ADC with SPI, currently I'm using MCP3551 and AD7798. If some ADC does not enable the MISO pin only when their CS input is asserted I will use one input buffer (5V) in their respective board for the MISO line, activated with the CS signal.

I will use a resistor in series with the output of the driving device for line termination as described at TI's LVC Designer's Guide.

For logic level translation I will use:

  • Quadruple bus buffers 74AHCT125 for 3.3V to 5.0V in the main board (SCK, CS and MOSI from MCU to the modules ADCs).

  • Octal bus transceivers 74LVC245A in the main board for 5.0V to 3.3V logic level voltage translation, from the modules ADCs MISO pins.

I've never worked with these buffers before. I can't figure if the 74LVC245A has open-collector outputs. Can I join and connect all the 74LVC245A outputs direct to the MCU MISO pin, like I do with MISO pins from 3.3V peripherals?

Edit: added tags.

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  • \$\begingroup\$ Any of these maybe? flikto.de/collections/breakouts-logic - Similar can be had at other shops too, of course. \$\endgroup\$
    – JimmyB
    May 4, 2016 at 13:33
  • \$\begingroup\$ Thanks, but since I'm using SPI I don't need a bi-directional logic-level-converter. \$\endgroup\$
    – Gilberto J
    May 4, 2016 at 14:40
  • \$\begingroup\$ I imagine you'd only really need a level translator on the MISO line, and then only one as the micro can drive one of the SPI lines directly, CS, SCK and MOSI are all out puts from the micro (I'm assuming the micro is 3.3V) and the 3.3V levels is probably enough to drive 5V SPI inputs. Not pretty, but as a quick hack, it may be fine \$\endgroup\$
    – Sam
    May 5, 2016 at 9:42
  • \$\begingroup\$ @Tom I'll use one level translator for each MISO because some SPI devices do not enable the MISO only when their CS input is asserted. So I figure by using a level translator for each MISO (enabled by their respective CS line) I wouldn't need to worry about that. Yes, the micro uses 3.3V. From one of the SPI slaves datasheet, the MCP3551, VIH (CS, SCK) min.=0.7VDD (3.5V). Maybe it also works with 3.3V, but I must make sure it always works. \$\endgroup\$
    – Gilberto J
    May 5, 2016 at 14:57
  • \$\begingroup\$ Ah, well, in that case, what about tying all the spi devices that use the same levels at the micro directly and just have one full set of level translators for the other rail. That way you're sort of running a single 3.3V SPI master bus and a single master 5V SPI bus, as opposed to each device having it's own translator. Would that be applicable to your system? \$\endgroup\$
    – Sam
    May 5, 2016 at 21:22

1 Answer 1

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The 74LVC245A has tri state outputs; taking the \$\overline {OE}\$ pin low enables communication from A to B or B to A (depending on the level on the DIR pin).

The outputs can have a state of High, Low and High impedance (Z).

You can therefore not tie the outputs together as these are push-pull outputs when enabled.

You could follow the '245A with a multiplexer to use a single pin at the micro.

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  • \$\begingroup\$ Also, look at the first paragraph of the datasheet, it clearly indicates that "OE controls the outputs so that the buses are effectively isolated." \$\endgroup\$
    – lucas92
    May 4, 2016 at 13:08
  • \$\begingroup\$ Thank you. I think I will use the 74LVC125A instead of 74LVC245A, since it has output enable pin for each line (which can be used with the respective CS line). \$\endgroup\$
    – Gilberto J
    May 4, 2016 at 14:39

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